Hi Maciej, On 16/05/15 01:44, Maciej W. Rozycki wrote: > On Wed, 13 May 2015, James Hogan wrote: > >> The TLB only matches the ASID when the global bit isn't set, so >> dump_tlb() shouldn't really be skipping global entries just because the >> ASID doesn't match. Fix the condition to read the TLB entry's global bit >> from EntryLo0. Note that after a TLB read the global bits in both >> EntryLo registers reflect the same global bit in the TLB entry. >> >> Signed-off-by: James Hogan <james.hogan@xxxxxxxxxx> >> Cc: Ralf Baechle <ralf@xxxxxxxxxxxxxx> >> Cc: linux-mips@xxxxxxxxxxxxxx >> --- >> arch/mips/lib/dump_tlb.c | 3 ++- >> 1 file changed, 2 insertions(+), 1 deletion(-) >> >> diff --git a/arch/mips/lib/dump_tlb.c b/arch/mips/lib/dump_tlb.c >> index 17d05caa776d..70e0a6bdb322 100644 >> --- a/arch/mips/lib/dump_tlb.c >> +++ b/arch/mips/lib/dump_tlb.c >> @@ -73,7 +73,8 @@ static void dump_tlb(int first, int last) >> */ >> if ((entryhi & ~0x1ffffUL) == CKSEG0) >> continue; >> - if ((entryhi & 0xff) != asid) >> + /* ASID takes effect in absense of global bit */ > > Typo here, s/absense/absence/. Thanks! > >> + if (!(entrylo0 & 1) && (entryhi & 0xff) != asid) > > Hmm, it looks like r3k_dump_tlb.c will need a similar update. I suggest Yes, quite possibly. Would you be happy to test such a patch (assuming you have r3000 hardware available)? Patch 1 should allow the code to be easily triggered. > using _PAGE_GLOBAL and ASID_MASK rather than hardcoded 1 and 0xff. Yeh, as you mentioned these describe the PTE rather than what goes in EntryLo. Perhaps it makes sense to have a few more TLB dependent definitions in mipsregs.h (patch 7 already adds a couple for RI/XI bits). Cheers James
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