This patchset improves dump_tlb.c to use proper hazard macros (for which
new macros are added for tlb reads), and to take into account the global
bit, the EHINV invalid bit, RI & XI bits, and XPA.
Patch 1 also adds a MIPS specific SysRq operation ('x') to dump the TLBs
on running CPUs. This is mainly for debug purposes, however I've
included it for completeness as an RFC patch, in case others find it
helpful.
Patches 2 & 3 add and make use of tlbr related hazard macros (which are
technically distinct, though identically implemented, to tlbw hazards).
Patches 4-6 improve the TLB entry matching so as to more closely match
which entries hardware treats as matching (taking the global and EHINV
bits into account).
Patches 7-8 improve the TLB printing to handle RI & XI bits (which show
up in the physical address at the moment), and XPA (where the top of the
physical address needs to be read from EntryLo registers with mfhc0).
Finally patch 9 is a trivial correction in a comment, that I noticed
while grepping around for XPA bits.
James Hogan (9):
MIPS: Add SysRq operation to dump TLBs on all CPUs
MIPS: hazards: Add hazard macros for tlb read
MIPS: dump_tlb: Use tlbr hazard macros
MIPS: dump_tlb: Refactor TLB matching
MIPS: dump_tlb: Take global bit into account
MIPS: dump_tlb: Take EHINV bit into account
MIPS: dump_tlb: Take RI/XI bits into account
MIPS: dump_tlb: Take XPA into account
MIPS: tlb-r4k: Fix PG_ELPA comment
arch/mips/include/asm/hazards.h | 52 ++++++++++++++++++++
arch/mips/include/asm/mipsregs.h | 11 +++++
arch/mips/kernel/Makefile | 1 +
arch/mips/kernel/sysrq.c | 77 +++++++++++++++++++++++++++++
arch/mips/lib/dump_tlb.c | 103 ++++++++++++++++++++++++---------------
arch/mips/mm/tlb-r4k.c | 2 +-
drivers/tty/sysrq.c | 1 +
7 files changed, 207 insertions(+), 40 deletions(-)
create mode 100644 arch/mips/kernel/sysrq.c
Cc: Ralf Baechle <ralf@xxxxxxxxxxxxxx>
Cc: Steven J. Hill <Steven.Hill@xxxxxxxxxx>
Cc: David Daney <ddaney@xxxxxxxxxxxxxxxxxx>
Cc: linux-mips@xxxxxxxxxxxxxx
--
2.3.6
