Re: [PATCH 1/4] MIPS: asm: r4kcache: Use correct base register for MIPS R6 cache flushes

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On Mon, 9 Mar 2015, Markos Chandras wrote:

> >  Since this operates on addresses shouldn't PTR_ADDIU be used instead?
> > 
> >   Maciej
> > 
> 
> I don't know. I thought PTR_ADDIU should be used for pointers but the
> arguments in these macros are "unsigned long".

 Hmm, good point.  I think we should match the C data type used even 
though we have an assumption that sizeof(long) == sizeof(void *), so your 
change looks right to me as it stands.

 I think we have a convention to separate `linux' from `asm' inclusions by 
an empty line though, so I suggest that you add one here:

> diff --git a/arch/mips/include/asm/r4kcache.h b/arch/mips/include/asm/r4kcache.h
> index 1b22d2da88a1..d329f7328bd4 100644
> --- a/arch/mips/include/asm/r4kcache.h
> +++ b/arch/mips/include/asm/r4kcache.h
> @@ -12,6 +12,7 @@
>  #ifndef _ASM_R4KCACHE_H
>  #define _ASM_R4KCACHE_H
>  
> +#include <linux/stringify.h>
>  #include <asm/asm.h>
>  #include <asm/cacheops.h>
>  #include <asm/compiler.h>

as well.  I can offer you my review tag if you repost the change with this 
trivial update.

  Maciej





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