On 03/05/2015 01:46 PM, Maciej W. Rozycki wrote:
> On Tue, 3 Mar 2015, Markos Chandras wrote:
>
>> Commit 934c79231c1b("MIPS: asm: r4kcache: Add MIPS R6 cache unroll
>> functions") added support for MIPS R6 cache flushes but it used the
>> wrong base address register to perform the flushes so the same lines
>> were flushed over and over. Moreover, replace the "addiu" instructions
>> with LONG_ADDIU so the correct base address is calculated for 64-bit
>> cores.
>
> Since this operates on addresses shouldn't PTR_ADDIU be used instead?
>
> Maciej
>
I don't know. I thought PTR_ADDIU should be used for pointers but the
arguments in these macros are "unsigned long".
--
markos
