Re: [PATCH 1/4] MIPS: asm: r4kcache: Use correct base register for MIPS R6 cache flushes

["Maciej W. Rozycki" <macro@xxxxxxxxxxxxxx>]

On Tue, 3 Mar 2015, Markos Chandras wrote:

> Commit 934c79231c1b("MIPS: asm: r4kcache: Add MIPS R6 cache unroll
> functions") added support for MIPS R6 cache flushes but it used the
> wrong base address register to perform the flushes so the same lines
> were flushed over and over. Moreover, replace the "addiu" instructions
> with LONG_ADDIU so the correct base address is calculated for 64-bit
> cores.

 Since this operates on addresses shouldn't PTR_ADDIU be used instead?

  Maciej