On Mon, Nov 03, 2014 at 08:08:58PM -0500, Joshua Kinard wrote: > I guess I could find a way to have the kernel trigger a non-fatal oops/dump the > registers on a bus error and get a look at the cause register to see if that > sheds any light on things. Doesn't a SIGBUS on MIPS typically mean that an > address wasn't aligned on a 32-bit boundary? Or could it also mean other things? > > I believe that the R10K is largely compatible with the R4K-style TLB setup, but > Ralf or someone else more knowledge in that area will have to verify. Maybe > the R10k-family CPUs need their own TLB routines, or what currently exists > needs modifications? I have not tried to understand the whole TLB thing in > MIPS yet, so that's a bit of voodoo to me. Voodoo that normally works a lot better than the conventional code it replaced! The R10000 TLB is basically the all dancing, all singing version of other MIPS TLBs. Noteworthy differences are that TLB hazards are handled in hardware and that the R10000 automatically detects multiple matching TLB entries on a TLB write in which case it will automatically invalidate the old entry before writing the new entry. It also is the only MIPS CPU to implement a c0_framemask register but to my understanding of that functionality the only software handling that register's functionality needs is initialization to zero essentially disabling it. The R10000 supports a maximum page size of 16M. Ralf
