On Wed, Nov 05, 2014 at 04:07:24AM -0500, Joshua Kinard wrote: > It was pointed out to me off list that this statement for the PageMask register > in the R10K manual may explain things: > > """TLB read and write operations use this register as either a source or a > destination; when virtual addresses are presented for translation into physical > address, the corresponding bits in the TLB identify which virtual address bits > among bits 24:13 are used in the comparison. When the Mask field is not one of > the values shown in Table 13-6, the operation of the TLB is undefined. The 0 > field is reserved; it must be written as zeroes, and returns zeroes when read.""" > > 2MB page sizes aren't explicitly listed in this table in the manual, so setting > bits 24:13 in PageMask might be leading to this "undefined behavior", which on > R12K might include the random bus errors/segfaults, and R14K triggers an IBE > that needs a cold reboot. All MIPS CPUs with a R4000-style TLB have this restriction. It's just that the behaviour of such bitmask values being undefined the resulting behviour is likely to differ between CPU types. 2MB pages will be loaded into the TLB as a pair of adjacent pair of 1MB pages. > The only other R10K system I have is the IP28, but I haven't gotten that to > boot up in a few years. Ralf
