On Tue, Apr 13, 2010 at 01:03:54PM +0800, Wu Zhangjin wrote: > This patch have broken the support to the MIPS variants whose > cpu_has_mips_r2 is 0 for the CAC_BASE and CKSEG0 is completely different > in these MIPSs. I've checked R4k and R10k manulas and the exception base is at CKSEG0, so about CPU we are talking ? And wouldn't it make for senso to have an extra define for the exception base then ? Thomas. -- Crap can work. Given enough thrust pigs will fly, but it's not necessary a good idea. [ RFC1925, 2.3 ]
