From: Wu Zhangjin <wuzhangjin@xxxxxxxxx> Loongson doesn't support MIPSR2, therefore, MIPSR2 vectored interrupts (cpu_has_vint) and MIPSR2 external interrupt controller mode (cpu_has_veic) are 0. Signed-off-by: Wu Zhangjin <wuzhangjin@xxxxxxxxx> --- .../asm/mach-loongson/cpu-feature-overrides.h | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h index 16210ce..675bd86 100644 --- a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h @@ -52,6 +52,8 @@ #define cpu_has_tx39_cache 0 #define cpu_has_userlocal 0 #define cpu_has_vce 0 +#define cpu_has_veic 0 +#define cpu_has_vint 0 #define cpu_has_vtag_icache 0 #define cpu_has_watch 1 -- 1.7.0
