Hello. Maciej W. Rozycki wrote:
So what is the issue with the size then? How big is the area?
I've already said: 4 gigs! At least in theory, actually it's 2 gigs due to
Oh, I mistook it for the base physical address, sorry.
That's 24 gigs. :-)
a device # being limited to 0 thru 19 (address bits 11 thru 30 are used as IDSELx).
It does not help too much with a 32-bit virtual address space indeed. Though I gather it has to be very sparsely populated as 16MiB is enough to cover the whole configuration space of a single PCI bus tree. Thus it has
Hm, maybe 16 MiB would be enough indeed, as the Alchemy CPUs are known to not support bus masters behind PCI bridges...
to be another example where the chip designer "forgot" to talk to software people. Or a shifter was traded for software performance and complexity. ;-)
I certainly agree here. :-)
There was no need to tell me about how KSEG0/1/2 work -- that's why I cosidered it wasting time. :-)
As I say -- the key is how you look at it. There are other readers on the list who may benefit; it is archived too. In this sense I can hardly consider it a waste of time. And it was fun to explain and no fun shall be ever considered of no use. :-)
Depends on the source of fun. :-)
Maciej
WBR, Sergei
