Hi Dominic Sweetman,
Thanks much for your inputs..
> > In R4000 & descendent processors, interrupt
> number 7
> > is being used for internal timer interrupt. From
> this
> > i understand that the timer interrupt is also
> maskable
> > when the IE bit in status register is cleared. If
> > somebody mask this interrupt for a long time
> > erroneously, then won't there be a problem in
> > maintaining the system time?
>
> Yes, there may be a long delay. So the standard way
> of using the
> onchip counter to generate a periodic interrupt is
> that the counter
> itself is allowed to free-run, keeping accurate
> time.
>
> The 'Compare' register is then incremented by a
> fixed amount.
>
> So long as the interrupt is not delayed by a whole
> tick, this keeps
> perfect time.
>
> I'm sure this is described in "See MIPS Run" - do
> you have a copy?
Yes, i have a copy. Have just started reading
this book.. I yet to get into the deep waters of the
MIPS..
May i know the purpose of the NMI interrupt and
in what way it differ from the timer interrupt.
Thanks much,
-karthi
> --
> Dominic Sweetman
> MIPS Technologies Inc
>
>
>
=====
The expert at anything was once a beginner
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