On Mon, Jun 03, 2024 at 08:58:10AM +0200, Krzysztof Kozlowski wrote: > On 03/06/2024 05:34, Jung Daehwan wrote: > > On Fri, May 31, 2024 at 10:12:03AM +0200, Krzysztof Kozlowski wrote: > >> On 31/05/2024 08:07, Daehwan Jung wrote: > >>> xHCI specification 5.1 "Register Conventions" states that 64 bit > >>> registers should be written in low-high order. All writing operations > >>> in xhci is done low-high order following the spec. > >> > >> What is high-low / low-high order? Are you talking about endianness? > >> > > > > It's not about endianness. It means 64 bit is written by 2 of 32 bit. > > It's when low-high / high-low order is needed. > > > >>> > >>> Add a new quirk to support workaround for high-low order. > >> > >> Why? If they should be written low-high, then why breaking the spec? Why > >> this cannot be deduced from compatible? > >> > > > > This quirk is for the controller that has a limitation in supporting > > separate ERSTBA_HI and ERSTBA_LO programming. > > > > I've copied below from other reply to tell why this is needed. > > > > I've found out the limitation of Synopsys dwc3 controller. This can work > > on Host mode using xHCI. A Register related to ERST should be written > > high-low order not low-high order. Registers are always written low-high order > > following xHCI spec.(64-bit written is done in each 2 of 32-bit) > > That's why new quirk is needed for workaround. This quirk is used not in > > dwc3 controller itself, but passed to xhci quirk eventually. That's because > > this issue occurs in Host mode using xHCI. > > > >> Which *upstream* hardware is affected? > >> > > > > dwc3 and xhci are affected. > > Which upstream controllers or SoCs are affected. You did not post any > user of this. > This issue is not specific on SoC side but dwc3 controller. I think it's better to add it to dwc3 directly but I can't find dts for dwc3. Dts for SoC, which uses dwc3 would be needed in this case, right? Best Regards, Jung Daehwan > Best regards, > Krzysztof > >
