On 31/05/2024 08:07, Daehwan Jung wrote: > xHCI specification 5.1 "Register Conventions" states that 64 bit > registers should be written in low-high order. All writing operations > in xhci is done low-high order following the spec. What is high-low / low-high order? Are you talking about endianness? > > Add a new quirk to support workaround for high-low order. Why? If they should be written low-high, then why breaking the spec? Why this cannot be deduced from compatible? Which *upstream* hardware is affected? Best regards, Krzysztof
