On 04/19/2016 02:10 PM, Felipe Balbi wrote:
Hi,
Kirill Dronov <cyrill.dronov@xxxxxxxxx> writes:
Is something definitely wrong with initialization and enumeration traces?
I'll go read them
> irq/19-dwc3-96 [000] d..2 824.785778: dwc3_event: event 00150301
Link State change -> RX.Detect
> irq/19-dwc3-96 [000] d..2 824.877339: dwc3_event: event 00040301
Link State Change SS.Disconnect
Not to SS.Disabled?
yes
> irq/19-dwc3-96 [000] d..2 824.877343: dwc3_event: event 00000301
Link State Change U0
> irq/19-dwc3-96 [000] d..2 824.881192: dwc3_event: event 00050301
Link State Change RX.Detect
> irq/19-dwc3-96 [000] d..2 824.885004: dwc3_event: event 00030301
Link State Change U3
> irq/19-dwc3-96 [000] d..2 825.218156: dwc3_event: event 00000101
USB Reset
> irq/19-dwc3-96 [000] d..2 825.229241: dwc3_event: event 00000201
Conncect Done
> irq/19-dwc3-96 [000] d..2 825.229248: dwc3_gadget: Enabling ep0out
enable ep0 with correct parameters
> irq/19-dwc3-96 [000] d..2 825.229252: dwc3_gadget_ep_cmd: ep0out: cmd 'Set Endpoint Configuration' [1] params 80000200 00000500 00000000
aram0: 64bytes wMaxPacketSize, Ignore Sequence Number set
param1: XferComplete and XferNotReady for physical ep0
param2: nothing
> irq/19-dwc3-96 [000] d..2 825.229257: dwc3_gadget: Command Complete --> 0
completes fine
> irq/19-dwc3-96 [000] d..2 825.229259: dwc3_gadget: Enabling ep0in
> irq/19-dwc3-96 [000] d..2 825.229260: dwc3_gadget_ep_cmd: ep0in: cmd 'Set Endpoint Configuration' [1] params 80000200 02000500 00000000
param0: 64bytes wMaxPacketSize, Ignore Sequence Number set
param1: XferComplete and XferNotReady for physical ep1
param2: nothing
> irq/19-dwc3-96 [000] d..2 825.229264: dwc3_gadget: Command Complete --> 0
completes fine
So, basically everything here is fine. There's nothing wrong
here. However, Right after these you get:
> irq/19-dwc3-96 [000] d..2 825.229265: dwc3_event: event 00000301
Link change U3 [3] -> U0 [0]
Host reports: " new high-speed USB device number XX using ehci-pci"
Host Sends USB_REQ_GET_DESCRIPTOR 3 times, gets r=-71. No events
detected on dwc3 side - this is the root issue.
Then host initiates device reset.
> irq/19-dwc3-96 [000] d..2 825.322544: dwc3_event: event 00050301
Link state change U0[0] -> Rx.Detect [5]
> irq/19-dwc3-96 [000] d..2 825.323162: dwc3_event: event 00000101
Reset interrupt
> irq/19-dwc3-96 [000] d..2 825.329773: dwc3_event: event 00000201
Conndone interrupt
> irq/19-dwc3-96 [000] d..2 825.329777: dwc3_gadget: Enabling ep0out
> irq/19-dwc3-96 [000] d..2 825.329782: dwc3_gadget_ep_cmd: ep0out: cmd 'Set Endpoint Configuration' [1] params 80000200 00000500 00000000
> irq/19-dwc3-96 [000] d..2 825.329786: dwc3_gadget: Command Complete --> 0
> irq/19-dwc3-96 [000] d..2 825.329788: dwc3_gadget: Enabling ep0in
> irq/19-dwc3-96 [000] d..2 825.329789: dwc3_gadget_ep_cmd: ep0in: cmd 'Set Endpoint Configuration' [1] params 80000200 02000500 00000000
> irq/19-dwc3-96 [000] d..2 825.329793: dwc3_gadget: Command Complete --> 0
All over again. And this repeats forever.
Well, actually it follows host enumeration process - with
usb_contorl_msg and hub_set_address returning -71,
and hub-initiated reset resulting in following sequence:
Link U0->Rx.Detect
reset interrupt
conndone interrupt
Link Rx.Detect -> U0
Did you load a gadget driver ?
Which gadget driver did you load ?
It's gadget zero. At least it's reported in dwc3_gadget_run_stop() -
see the last line in dwc3-init.trace:
insmod-95 [000] d..2 603.695374: dwc3_gadget: gadget zero data
soft-connect
okay, I really have no idea what's going on with your SoC. This works
fine with skylake, broxton and some other Intel SoCs I have around.
I have E3800 only (
If this fails the same way with WindRiver provided kernel, I'd say you
should really contact them because I have no information on this SoC
you're using.
Just to be sure, you're using vanilla v4.6-rc4 ?
vanilla 4.6.0-rc3+
no changes whatsoever
2 changes:
1) added platform drivers in linux/drivers/platform/
should not influence dwc3
2) the only dwc3 -related change is in dwc3_pci_quirks():
I need different "baytrail" quirk - smsc 3310 does not have CS. So I
request appropriate gpio and set it "out high" to get phy out of reset.
ULPI clocks are enabled earlier in bootcode (via GEN_REGRW1) - so don't
handle it in dwc3 code.
on top of mainline, right ?
upstream HEAD is commit 1c74a7f812b135d3df41d7c3671b647aed6467bf
---
thank you,
Kirill
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