On Mon, Jan 20, 2014 at 11:26:02AM +0100, Matthieu CASTET wrote: > Le Sat, 18 Jan 2014 09:03:01 +0100, > Michael Grzeschik <mgr@xxxxxxxxxxxxxx> a écrit : > > > On Fri, Jan 17, 2014 at 05:15:49PM +0100, Matthieu CASTET wrote: > > > How many fifo have your controller (hw_ep_max) ? > > > > It's MX28. For this hw_ep_max is 16. > > > > > When you say fifo on position 8, you mean in software (in ci_hw_ep > > > array), but not in hardware (ENDPTCTRLx) ? > > > > Yes. In the code "i" is the index of the hwep array. AFAIK the array is > > organized like this; > > > > i == [0:7] out endpoints > > i == [8:15] in endpoints. > > > > Therefor index 0 is ep0out and index 8 is ep0in. > > > Could you try the attached patch ? > > The SETUPSTAT register is only 16 bits. For index 8 (ep_to_bit(8) = 16) > we shouldn't read it. Yes, the ep_to_bit is not suitable for clear ENDPTSETUPSTAT. In fact, we only need to clear bit0 at ENDPTSETUPSTAT for ep0out since we only receive setup packet at ep0out. Michael's problem is too many warning message for ep0in, the possible reason is ENDPTSETUPSTAT BIT(16) is not zero at that time (it is strange!). In fact, for ep0in complete handler, it should do noop except clear the complete status and notify class driver. I think you patch can solve Michael's problem currently. I will split ep0 and non-ep0 complete handler soon according your suggestion below. Peter > > > Matthieu > > PS : the code for handling ctrl endpoint is a bit messy. We should > split isr_tr_complete_handler in isr_tr_complete_handler and > isr_tr_setup_handler. > -- Best Regards, Peter Chen -- To unsubscribe from this list: send the line "unsubscribe linux-usb" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
