Le Sat, 18 Jan 2014 09:03:01 +0100, Michael Grzeschik <mgr@xxxxxxxxxxxxxx> a écrit : > On Fri, Jan 17, 2014 at 05:15:49PM +0100, Matthieu CASTET wrote: > > How many fifo have your controller (hw_ep_max) ? > > It's MX28. For this hw_ep_max is 16. > > > When you say fifo on position 8, you mean in software (in ci_hw_ep > > array), but not in hardware (ENDPTCTRLx) ? > > Yes. In the code "i" is the index of the hwep array. AFAIK the array is > organized like this; > > i == [0:7] out endpoints > i == [8:15] in endpoints. > > Therefor index 0 is ep0out and index 8 is ep0in. > Could you try the attached patch ? The SETUPSTAT register is only 16 bits. For index 8 (ep_to_bit(8) = 16) we shouldn't read it. Matthieu PS : the code for handling ctrl endpoint is a bit messy. We should split isr_tr_complete_handler in isr_tr_complete_handler and isr_tr_setup_handler.
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