Hi, Geert,
On 24.01.2025 14:56, Geert Uytterhoeven wrote:
> Hi Claudiu,
>
> On Mon, Jan 20, 2025 at 2:09 PM Claudiu <claudiu.beznea@xxxxxxxxx> wrote:
>> From: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
>>
>> Add DT overlay for SCIF1 (of the Renesas RZ/G3S SoC) routed through the
>> PMOD1_3A interface available on the Renesas RZ SMARC Carrier II board.
>>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
>> ---
>>
>> Changes in v4:
>> - rename overlay name to r9a08g045s33-smarc-pmod1-type-3a
>> - add note about the needed switches for SCIF1
>> - guard the scif1 node with #if SW_CONFIG3 == SW_ON && SW_OPT_MUX4 == SW_ON
>> - dropped the alias section from the overlay file and move it
>> the board file
>> - document SW_OPT_MUX4 switch
>
> Thanks for the update!
>
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/renesas/r9a08g045s33-smarc-pmod1-type-3a.dtso
>> @@ -0,0 +1,48 @@
>> +// SPDX-License-Identifier: GPL-2.0
>
> Would you mind if I changed this to (GPL-2.0-only OR BSD-2-Clause) while
> applying?
Not at all. Thank you for taking care of it.
>
>> +&pinctrl {
>> + scif1_pins: scif1-pins {
>> + pinmux = <RZG2L_PORT_PINMUX(14, 0, 1)>, /* TXD */
>> + <RZG2L_PORT_PINMUX(14, 1, 1)>, /* RXD */
>> + <RZG2L_PORT_PINMUX(16, 0, 1)>, /* CTS */
>> + <RZG2L_PORT_PINMUX(16, 1, 1)>; /* RTS */
>
> CTS# and RTS#
>
>> + };
>> +};
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
> i.e. will queue in renesas-devel for v6.15.
>
> Gr{oetje,eeting}s,
>
> Geert
>
