From: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
Add DT overlay for SCIF1 (of the Renesas RZ/G3S SoC) routed through the
PMOD1_3A interface available on the Renesas RZ SMARC Carrier II board.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
---
Changes in v4:
- rename overlay name to r9a08g045s33-smarc-pmod1-type-3a
- add note about the needed switches for SCIF1
- guard the scif1 node with #if SW_CONFIG3 == SW_ON && SW_OPT_MUX4 == SW_ON
- dropped the alias section from the overlay file and move it
the board file
- document SW_OPT_MUX4 switch
Changes in v3:
- none
Changes in v2:
- none
arch/arm64/boot/dts/renesas/Makefile | 3 ++
.../r9a08g045s33-smarc-pmod1-type-3a.dtso | 48 +++++++++++++++++++
.../boot/dts/renesas/rzg3s-smarc-switches.h | 8 ++++
arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 1 +
4 files changed, 60 insertions(+)
create mode 100644 arch/arm64/boot/dts/renesas/r9a08g045s33-smarc-pmod1-type-3a.dtso
diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index 928635f2e76b..ef7f7b55145d 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -143,6 +143,9 @@ r9a07g054l2-smarc-cru-csi-ov5645-dtbs := r9a07g054l2-smarc.dtb r9a07g054l2-smarc
dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-smarc-cru-csi-ov5645.dtb
dtb-$(CONFIG_ARCH_R9A08G045) += r9a08g045s33-smarc.dtb
+dtb-$(CONFIG_ARCH_R9A07G043) += r9a08g045s33-smarc-pmod1-type-3a.dtbo
+r9a08g045s33-smarc-pmod1-type-3a-dtbs := r9a08g045s33-smarc.dtb r9a08g045s33-smarc-pmod1-type-3a.dtbo
+dtb-$(CONFIG_ARCH_R9A07G043) += r9a08g045s33-smarc-pmod1-type-3a.dtb
dtb-$(CONFIG_ARCH_R9A09G011) += r9a09g011-v2mevk2.dtb
diff --git a/arch/arm64/boot/dts/renesas/r9a08g045s33-smarc-pmod1-type-3a.dtso b/arch/arm64/boot/dts/renesas/r9a08g045s33-smarc-pmod1-type-3a.dtso
new file mode 100644
index 000000000000..e4cb4449f190
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a08g045s33-smarc-pmod1-type-3a.dtso
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the RZ/G3S SMARC Carrier II EVK PMOD parts
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ *
+ *
+ * [Connection]
+ *
+ * SMARC Carrier II EVK
+ * +--------------------------------------------+
+ * |PMOD1_3A (PMOD1 PIN HEADER) |
+ * | SCIF1_CTS# (pin1) (pin7) PMOD1_GPIO10 |
+ * | SCIF1_TXD (pin2) (pin8) PMOD1_GPIO11 |
+ * | SCIF1_RXD (pin3) (pin9) PMOD1_GPIO12 |
+ * | SCIF1_RTS# (pin4) (pin10) PMOD1_GPIO13 |
+ * | GND (pin5) (pin11) GND |
+ * | PWR_PMOD1 (pin6) (pin12) GND |
+ * +--------------------------------------------+
+ *
+ * The following switches should be set as follows for SCIF1:
+ * - SW_CONFIG2: ON
+ * - SW_OPT_MUX4: ON
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+#include "rzg3s-smarc-switches.h"
+
+&pinctrl {
+ scif1_pins: scif1-pins {
+ pinmux = <RZG2L_PORT_PINMUX(14, 0, 1)>, /* TXD */
+ <RZG2L_PORT_PINMUX(14, 1, 1)>, /* RXD */
+ <RZG2L_PORT_PINMUX(16, 0, 1)>, /* CTS */
+ <RZG2L_PORT_PINMUX(16, 1, 1)>; /* RTS */
+ };
+};
+
+#if SW_CONFIG3 == SW_ON && SW_OPT_MUX4 == SW_ON
+&scif1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&scif1_pins>;
+ uart-has-rtscts;
+ status = "okay";
+};
+#endif
diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h b/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h
index 514a8a6dc013..9766cea55dc6 100644
--- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h
+++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h
@@ -29,4 +29,12 @@
#define SW_CONFIG2 SW_OFF
#define SW_CONFIG3 SW_ON
+/*
+ * SW_OPT_MUX[x] switches' states:
+ * @SW_OPT_MUX4:
+ * SW_OFF - The SMARC SER0 signals are routed to M.2 Key E UART
+ * SW_ON - The SMARC SER0 signals are routed to PMOD1
+ */
+#define SW_OPT_MUX4 SW_ON
+
#endif /* __RZG3S_SMARC_SWITCHES__ */
diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi
index 0851e0b7ed40..5e044a4d0234 100644
--- a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi
@@ -12,6 +12,7 @@
/ {
aliases {
i2c0 = &i2c0;
+ serial0 = &scif1;
serial1 = &scif3;
serial3 = &scif0;
mmc1 = &sdhi1;
--
2.43.0
