On Sat, Sep 14, 2024 at 10:08 PM Serge Semin <fancer.lancer@xxxxxxxxx> wrote: > > On Sat, Sep 14, 2024 at 10:06:16PM +0300, Serge Semin wrote: > > Hi Andy > > > > On Sat, Sep 14, 2024 at 09:50:48PM +0300, Andy Shevchenko wrote: > > > On Mon, Aug 05, 2024 at 03:25:35PM +0300, Serge Semin wrote: > > > > On Sat, Aug 03, 2024 at 09:29:54PM +0200, Andy Shevchenko wrote: > > > > > On Fri, Aug 2, 2024 at 9:51 AM Serge Semin <fancer.lancer@xxxxxxxxx> wrote: > > > > > > > > > > > > The main goal of this series is to fix the data disappearance in case of > > > > > > the DW UART handled by the DW AHB DMA engine. The problem happens on a > > > > > > portion of the data received when the pre-initialized DEV_TO_MEM > > > > > > DMA-transfer is paused and then disabled. The data just hangs up in the > > > > > > DMA-engine FIFO and isn't flushed out to the memory on the DMA-channel > > > > > > suspension (see the second commit log for details). On a way to find the > > > > > > denoted problem fix it was discovered that the driver doesn't verify the > > > > > > peripheral device address width specified by a client driver, which in its > > > > > > turn if unsupported or undefined value passed may cause DMA-transfer being > > > > > > misconfigured. It's fixed in the first patch of the series. > > > > > > > > > > > > In addition to that three cleanup patches follow the fixes described above > > > > > > in order to make the DWC-engine configuration procedure more coherent. > > > > > > First one simplifies the CTL_LO register setup methods. Second and third > > > > > > patches simplify the max-burst calculation procedure and unify it with the > > > > > > rest of the verification methods. Please see the patches log for more > > > > > > details. > > > > > > > > > > > > Final patch is another cleanup which unifies the status variables naming > > > > > > in the driver. > > > > > > > > > > Acked-by: Andy Shevchenko <andy@xxxxxxxxxx> > > > > > > > > Awesome! Thanks. > > > > > > Not really :-) > > > This series broke iDMA32 + SPI PXA2xx on Intel Merrifield. > > > > Damn. Sorry to hear that.( > > > > > I haven't > > > had time to investigate further, but rolling back all patches helps. > > > > > > +Cc: Ferry who might also test and maybe investigate as he reported the > > > issue to me initially. > > > > Ferry, could you please roll back the series patch-by-patch to find > > out the particular commit to blame? > > Plus to that it would be nice to have some log/info/details/etc about > what exactly is happening. For me with patch spitest -l -s1000000 -b128 /dev/spidev5.1 SPI: [mode 0x20, bits_per_word 8, speed 1000000 Hz] [ 164.525604] pxa2xx_spi_pci 0000:00:07.1: DMA slave config failed [ 164.536105] pxa2xx_spi_pci 0000:00:07.1: failed to get DMA TX descriptor [ 164.543213] spidev spi-SPT0001:00: SPI transfer failed: -16 [ 164.550140] spi_master spi5: failed to transfer one message from queue [ 164.557126] spi_master spi5: noqueue transfer failed spitest: SPI transfer failed in iteration #0: Device or resource busy Without spitest -s 1000000 -b 128 -l /dev/spidev5.1 SPI: [mode 0x20, bits_per_word 8, speed 1000000 Hz] SEND: [00000000] ff 97 d0 54 d5 69 85 6e ca e7 b3 e1 a1 e5 1a 9d ... RECV: [00000000] ff 97 d0 54 d5 69 85 6e ca e7 b3 e1 a1 e5 1a 9d ... `spitest` is our internal tool, so what it does there is: 1) opens SPI device for speed 1MHz in loopback mode 2) generates 128 byte of random data 3) tries to send and receive them 4) compares I believe the similar behaviour can be achieved with the one that is in the kernel tree. -- With Best Regards, Andy Shevchenko
