Hi Andy, On Sat, Aug 03, 2024 at 09:29:54PM +0200, Andy Shevchenko wrote: > On Fri, Aug 2, 2024 at 9:51 AM Serge Semin <fancer.lancer@xxxxxxxxx> wrote: > > > > The main goal of this series is to fix the data disappearance in case of > > the DW UART handled by the DW AHB DMA engine. The problem happens on a > > portion of the data received when the pre-initialized DEV_TO_MEM > > DMA-transfer is paused and then disabled. The data just hangs up in the > > DMA-engine FIFO and isn't flushed out to the memory on the DMA-channel > > suspension (see the second commit log for details). On a way to find the > > denoted problem fix it was discovered that the driver doesn't verify the > > peripheral device address width specified by a client driver, which in its > > turn if unsupported or undefined value passed may cause DMA-transfer being > > misconfigured. It's fixed in the first patch of the series. > > > > In addition to that three cleanup patches follow the fixes described above > > in order to make the DWC-engine configuration procedure more coherent. > > First one simplifies the CTL_LO register setup methods. Second and third > > patches simplify the max-burst calculation procedure and unify it with the > > rest of the verification methods. Please see the patches log for more > > details. > > > > Final patch is another cleanup which unifies the status variables naming > > in the driver. > > Acked-by: Andy Shevchenko <andy@xxxxxxxxxx> Awesome! Thanks. -Serge(y) > > -- > With Best Regards, > Andy Shevchenko
