Hi Biju,
On Wed, Apr 12, 2023 at 4:51 PM Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> SCIFA IP on RZ/G2L SoC has the same signal for both interrupt
> and DMA transfer request. Setting DMARS register for DMA transfer
> makes the signal to work as a DMA transfer request signal and
> subsequent interrupt requests to the interrupt controller
> are masked. Similarly clearing DMARS register makes signal to work as
> interrupt signal and subsequent interrupt requests to the interrupt
> controller are unmasked.
>
> Add SCIFA DMA tx support for RZ/G2L alike SoCs by disabling TXI line
> interrupt and setting DMARS registers by DMA api for DMA transfer request.
>
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> ---
> v3->v4:
> * Updated commit description by removing tx end interrupt.
Thanks for the update!
> --- a/drivers/tty/serial/sh-sci.c
> +++ b/drivers/tty/serial/sh-sci.c
> @@ -588,12 +588,17 @@ static void sci_start_tx(struct uart_port *port)
>
> if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
> dma_submit_error(s->cookie_tx)) {
> + if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE)
> + /* Switch irq from SCIF to DMA */
> + disable_irq(s->irqs[SCIx_TXI_IRQ]);
Please wrap this block inside curly braces.
> +
The rest LGTM, so
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
