On Wed, Apr 12, 2023 at 4:51 PM Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> SCIFA IP on RZ/G2L SoC has the same signal for both interrupt
> and DMA transfer request. Setting DMARS register for DMA transfer
> makes the signal to work as a DMA transfer request signal and
> subsequent interrupt requests to the interrupt controller
> are masked. Similarly clearing DMARS register makes signal to work as
> interrupt signal and subsequent interrupt requests to the interrupt
> controller are unmasked.
>
> Add SCIFA DMA rx support for RZ/G2L alike SoCs by disabling RXI line
> interrupt and setting DMARS registers by DMA api for DMA transfer request.
>
> Apart from this, we must set FIFO trigger to 1 for the expected behavior
> of the receive transmission.
>
> While at it replace the parameter irq to s->irqs[SCIx_RXI_IRQ] in
> disable_irq_nosync() to match enable_irq() in sci_dma_rx_reenable_irq().
>
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> ---
> v3->4:
> * Updated commit description.
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
