On 7/14/22 14:14, Datta, Shubhrajyoti wrote:
[AMD Official Use Only - General]
-----Original Message-----
From: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
Sent: Thursday, July 14, 2022 5:29 PM
To: Michal Simek <michal.simek@xxxxxxxxxx>; Shubhrajyoti Datta
<shubhrajyoti.datta@xxxxxxxxx>; Rob Herring <robh@xxxxxxxxxx>; Krzysztof
Kozlowski <krzysztof.kozlowski+dt@xxxxxxxxxx>
Cc: Shubhrajyoti Datta <shubhraj@xxxxxxxxxx>; linux-serial@xxxxxxxxxxxxxxx;
devicetree@xxxxxxxxxxxxxxx; gregkh@xxxxxxxxxxxxxxxxxxx; Srinivas Goud
<sgoud@xxxxxxxxxx>
Subject: Re: [PATCH 1/2] dt-bindings: serial: pl011: Add 'arm,xlnx-uart'
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On 14/07/2022 12:55, Michal Simek wrote:
Hi Rob and Krzysztof,
On 6/14/22 14:21, Shubhrajyoti Datta wrote:
<snip>
No, I don't know what the differences are in your h/w. You have ID
registers, but changed the IP and didn't change the ID registers?
How has the IP changed?
The IP is not changed and the ID registers are not updated.
The limitation is coming from the AXI port that the IP is connected to.
The axi port is allowing only the 32 bit access.
The same information will be updated in the Versal TRM.
Can you please give us your recommendation how to process with this?
Unfortunately I don't think that anyone remembers context from last year,
especially me who was not Cced. Rob responded at end of March and it took
two months to get back any answer. Such slow response time from submitter
does not help to stay in the context. :(
I had to contact the hardware team and get the details on the issue it took me sometime to get a response.
I will summarize
We are using the ip from ARM but the AXI port that we hooked has a limitation that it allows only 32 bit accesses.
So to tide over the and differentiate I am adding a new compatible arm,xlnx-uart.
ok.
Shubhrajyoti: Please send this series again with updated commit message in 1/2
which contains information you provided here. That means it will be v2 version.
Thanks,
Michal
