On Tue, Nov 16, 2021 at 04:47:45PM +0530, Shubhrajyoti Datta wrote: > Add support for Uart used in Xilinx Versal SOCs as a platform > device. No. Why would we want to do that? > > Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xxxxxxxxxx> > Signed-off-by: Raviteja Narayanam <raviteja.narayanam@xxxxxxxxxx> > --- > Documentation/devicetree/bindings/serial/pl011.yaml | 10 +++++++--- > 1 file changed, 7 insertions(+), 3 deletions(-) > > diff --git a/Documentation/devicetree/bindings/serial/pl011.yaml b/Documentation/devicetree/bindings/serial/pl011.yaml > index 5ea00f8a283d..6c73923dd15e 100644 > --- a/Documentation/devicetree/bindings/serial/pl011.yaml > +++ b/Documentation/devicetree/bindings/serial/pl011.yaml > @@ -24,9 +24,13 @@ select: > > properties: > compatible: > - items: > - - const: arm,pl011 > - - const: arm,primecell > + oneOf: > + - items: > + - const: arm,pl011 > + - const: arm,primecell > + - items: > + - const: arm,pl011 > + - const: arm,xlnx-uart # xilinx uart as platform device 'arm,primecell' means the block has ID registers. Are you saying this implementation doesn't? > > reg: > maxItems: 1 > -- > 2.25.1 > >
