On Wed, 30 Mar 2022, Miquel Raynal wrote:
> From: Phil Edworthy <phil.edworthy@xxxxxxxxxxx>
>
> DW based controllers like the one on Renesas RZ/N1 must be programmed as
> flow controllers when using DMA.
>
> * Table 11.45 of the system manual, "Flow Control Combinations", states
> that using UART with DMA requires setting the DMA in the peripheral
> flow controller mode regardless of the direction.
>
> * Chapter 11.6.1.3 of the system manual, "Basic Interface Definitions",
> explains that the burst size in the above case must be configured in
> the peripheral's register DEST/SRC_BURST_SIZE.
>
> Experiments shown that upon Rx timeout, the DMA transaction needed to be
> manually cleared as well.
>
> Signed-off-by: Phil Edworthy <phil.edworthy@xxxxxxxxxxx>
> Co-developed-by: Miquel Raynal <miquel.raynal@xxxxxxxxxxx>
> Signed-off-by: Miquel Raynal <miquel.raynal@xxxxxxxxxxx>
> ---
> drivers/tty/serial/8250/8250_dw.c | 64 +++++++++++++++++++++++++++++++
> 1 file changed, 64 insertions(+)
>
> diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
> index a156c6d2f866..977a473535e8 100644
> --- a/drivers/tty/serial/8250/8250_dw.c
> +++ b/drivers/tty/serial/8250/8250_dw.c
> @@ -34,14 +34,26 @@
>
> /* Offsets for the DesignWare specific registers */
> #define DW_UART_USR 0x1f /* UART Status Register */
> +#define DW_UART_DMASA 0xa8 /* DMA Software Ack */
> +
> +#define RZN1_UART_TDMACR 0x10c /* DMA Control Register Transmit Mode */
> +#define RZN1_UART_RDMACR 0x110 /* DMA Control Register Receive Mode */
>
> /* DesignWare specific register fields */
> #define DW_UART_MCR_SIRE BIT(6)
>
> +/* Renesas specific register fields */
> +#define RZN1_UART_xDMACR_DMA_EN BIT(0)
> +#define RZN1_UART_xDMACR_1_WORD_BURST (0 << 1)
> +#define RZN1_UART_xDMACR_4_WORD_BURST (1 << 1)
> +#define RZN1_UART_xDMACR_8_WORD_BURST (3 << 1)
> +#define RZN1_UART_xDMACR_BLK_SZ(x) ((x) << 3)
> +
> /* Quirks */
> #define DW_UART_QUIRK_OCTEON BIT(0)
> #define DW_UART_QUIRK_ARMADA_38X BIT(1)
> #define DW_UART_QUIRK_SKIP_SET_RATE BIT(2)
> +#define DW_UART_QUIRK_IS_DMA_FC BIT(3)
>
> static inline struct dw8250_data *clk_to_dw8250_data(struct notifier_block *nb)
> {
> @@ -224,6 +236,7 @@ static int dw8250_handle_irq(struct uart_port *p)
> struct dw8250_data *d = to_dw8250_data(p->private_data);
> unsigned int iir = p->serial_in(p, UART_IIR);
> bool rx_timeout = (iir & 0x3f) == UART_IIR_RX_TIMEOUT;
> + unsigned int quirks = d->pdata->quirks;
> unsigned int status;
> unsigned long flags;
>
> @@ -247,6 +260,15 @@ static int dw8250_handle_irq(struct uart_port *p)
> spin_unlock_irqrestore(&p->lock, flags);
> }
>
> + /* Manually stop the Rx DMA transfer when acting as flow controller */
> + if (up->dma && up->dma->rx_running && rx_timeout && quirks & DW_UART_QUIRK_IS_DMA_FC) {
> + status = p->serial_in(p, UART_LSR);
> + if (status & (UART_LSR_DR | UART_LSR_BI)) {
> + writel(0, p->membase + RZN1_UART_RDMACR);
> + writel(1, p->membase + DW_UART_DMASA);
Currently there is serial_out(), dw8250_writel_ext(), and a few writel()s
too for writing to registers. It would be nice to move towards more
homogeneous approach rather than adding more writel()s.
I suggest dw8250_writel_ext() is moved to dwlib.h. Then it could be used
here (and dw8250_readl_ext() too should be moved but IIRC there wasn't
any reads added by this series).
--
i.
