On Thu, 7 May 2020, Arnd Bergmann wrote:
> > The patch 92d7223a74235054f2aa7227d207d9c57f84dca0 ("alpha: io: reorder
> > barriers to guarantee writeX() and iowriteX() ordering #2") broke boot on
> > the Alpha Avanti platform.
> >
> > The patch changes timing between accesses to the ISA bus, in particular,
> > it reduces the time between "write" access and a subsequent "read" access.
> >
> > This causes lock-up when accessing the real time clock and serial ports.
> >
> > This patch fixes the bug by adding a memory barrier after the functions
> > that access the ISA ports - outb, outw, outl. The barrier causes that
> > there is some delay between the write to an IO port and a subsequent read.
There is no delay guarantee, just an in-order completion guarantee:
#define mb() __asm__ __volatile__("mb": : :"memory")
MB is a hardware memory barrier instruction.
> Based on your earlier explanations, I would mention here that the barrier
> avoids the back-to-back I/O instructions on the bus that seem to be causing
> the problem. As I understand it (having very little alpha specific knowledge),
> they should prevent them by design. However if you are sure it's just the
> added delay rather than any actual barrier effect, that would also be worth
> pointing out.
Alpha is weakly ordered, also WRT MMIO. Writing a simple test program to
poke directly (e.g. using `ioremap' and then inline asm on the location
obtained) at RTC and UART registers would be a good way to determine what
is really going on here.
Maciej
