On Thu, May 7, 2020 at 10:06 AM Mikulas Patocka <mpatocka@xxxxxxxxxx> wrote:
> On Wed, 6 May 2020, Mikulas Patocka wrote:
> > On Wed, 6 May 2020, Arnd Bergmann wrote:
> > > On Wed, May 6, 2020 at 1:21 PM Mikulas Patocka <mpatocka@xxxxxxxxxx> wrote:
> > >
> > > > /*
> > > > * The yet supported machines all access the RTC index register via
> > > > * an ISA port access but the way to access the date register differs ...
> > > > + *
> > > > + * The ISA bus on Alpha Avanti doesn't like back-to-back accesses,
> > > > + * we need to add a small delay.
> > > > */
> > > > #define CMOS_READ(addr) ({ \
> > > > outb_p((addr),RTC_PORT(0)); \
> > > > +udelay(2); \
> > > > inb_p(RTC_PORT(1)); \
> > >
> > >
> > > The inb_p() / outb_p() functions are meant to already have a delay in them,
> > > maybe we should just add it there for alpha?
> > >
> > > Arnd
> >
> > Yes, that is possible too - it fixes the real time clock hang for me.
> >
> >
> > -#define inb_p inb
> > -#define inw_p inw
> > -#define inl_p inl
> > +#define inb_p(x) (ndelay(300), inb(x))
> > +#define inw_p(x) (ndelay(300), inw(x))
> > +#define inl_p(x) (ndelay(300), inl(x))
> > #define outb_p outb
> > #define outw_p outw
> > #define outl_p outl
>
> 300ns was too low. We need at least 1400ns to fix the hang reliably.
Are you sure that it is in fact the timing that is important here and not
a barrier? I see that inb() is written in terms of readb(), but the
barrier requirements for I/O space are a bit different from those
on PCI memory space.
In the example you gave first, there is a an outb_p() followed by inb_p().
These are normally serialized by the bus, but I/O space also has the
requirement that an outb() completes before we get to the next
instruction (non-posted write), while writeb() is generally posted and
only needs a barrier before the write rather than both before and after
like outb.
Arnd
