The patch 92d7223a74235054f2aa7227d207d9c57f84dca0 ("alpha: io: reorder
barriers to guarantee writeX() and iowriteX() ordering #2") broke boot on
the Alpha Avanti platform.
The patch changes timing between accesses to the ISA bus, in particular,
it reduces the time between "write" access and a subsequent "read" access.
This causes lock-up when accessing the real time clock and serial ports.
This patch fixes the real time clock by adding a small delay between
outb_p and inb_p.
Note that we don't have to add the delay to CMOS_WRITE, because it
consists of two write accesses and they already have mb() between them.
Signed-off-by: Mikulas Patocka <mpatocka@xxxxxxxxxx>
Fixes: 92d7223a7423 ("alpha: io: reorder barriers to guarantee writeX() and iowriteX() ordering #2")
Cc: stable@xxxxxxxxxxxxxxx # v4.17+
---
arch/alpha/include/asm/mc146818rtc.h | 4 ++++
1 file changed, 4 insertions(+)
Index: linux-stable/arch/alpha/include/asm/mc146818rtc.h
===================================================================
--- linux-stable.orig/arch/alpha/include/asm/mc146818rtc.h 2020-05-05 20:48:30.000000000 +0200
+++ linux-stable/arch/alpha/include/asm/mc146818rtc.h 2020-05-05 21:05:53.000000000 +0200
@@ -15,9 +15,13 @@
/*
* The yet supported machines all access the RTC index register via
* an ISA port access but the way to access the date register differs ...
+ *
+ * The ISA bus on Alpha Avanti doesn't like back-to-back accesses,
+ * we need to add a small delay.
*/
#define CMOS_READ(addr) ({ \
outb_p((addr),RTC_PORT(0)); \
+udelay(2); \
inb_p(RTC_PORT(1)); \
})
#define CMOS_WRITE(val, addr) ({ \
