On Sun, 10 May 2020, Maciej W. Rozycki wrote: > On Thu, 7 May 2020, Arnd Bergmann wrote: > > > > Do you think that all the "in[bwl]" and "out[bwl]" macros on alpha should > > > be protected by two memory barriers, to emulate the x86 behavior? > > > > That's what we do on some other architectures to emulate the non-posted > > behavior of out[bwl], as required by PCI. I can't think of any reasons to > > have a barrier before in[bwl], or after write[bwl], but we generally want > > one after out[bwl] > > Alpha is weakly ordered, also WRT MMIO. The details are a bit obscure > (and were discussed before in a previous iteration of these patches), but > my understanding is multiple writes can be merged and writes can be > reordered WRT reads, even on UP. It's generally better for performance to We discussed it some times ago, and the conclusion was that reads and writes to the same device are not reordered on Alpha. Reads and writes to different devices or to memory may be reordered. In these problematic cases, we only access serial port or real time clock using a few ports (and these devices don't have DMA, so there's not any interaction with memory) - so I conclude that it is timing problem and not I/O reordering problem. > have ordering barriers before MMIO operations rather than afterwards, > unless a completion barrier is also required (e.g. for level-triggered > interrupt acknowledgement). > > Currently we don't fully guarantee that `outX' won't be posted (from > memory-barriers.txt): > > " (*) inX(), outX(): > [...] > Device drivers may expect outX() to emit a non-posted write transaction > that waits for a completion response from the I/O peripheral before > returning. This is not guaranteed by all architectures and is therefore > not part of the portable ordering semantics." > > Maciej Mikulas
