From: Fabio Estevam <fabio.estevam@xxxxxxxxxxxxx>
Disable interrupts before requesting them in order to fix a kernel oops
after lauching a kernel via kexec.
Tested on a imx6sl-evk board.
Signed-off-by: Fabio Estevam <fabio.estevam@xxxxxxxxxxxxx>
---
Changes since v1:
- Do not clear the whole UCR1 register. Only clear the irq bits as
suggested by Uwe
- Enable/disable the ipg clock to access the UCR1 register
drivers/tty/serial/imx.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
index 2c90dc3..0f29cd059 100644
--- a/drivers/tty/serial/imx.c
+++ b/drivers/tty/serial/imx.c
@@ -1902,7 +1902,7 @@ static int serial_imx_probe(struct platform_device *pdev)
{
struct imx_port *sport;
void __iomem *base;
- int ret = 0;
+ int ret = 0, reg;
struct resource *res;
int txirq, rxirq, rtsirq;
@@ -1957,6 +1957,17 @@ static int serial_imx_probe(struct platform_device *pdev)
sport->port.uartclk = clk_get_rate(sport->clk_per);
+ /* For register access, we only need to enable the ipg clock. */
+ clk_prepare_enable(sport->clk_ipg);
+
+ /* Disable interrupts before requesting them */
+ reg = readl(sport->port.membase + UCR1);
+ reg &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN |
+ UCR1_TXMPTYEN | UCR1_RTSDEN);
+ writel(reg, sport->port.membase + UCR1);
+
+ clk_disable_unprepare(sport->clk_ipg);
+
/*
* Allocate the IRQ(s) i.MX1 has three interrupts whereas later
* chips only have one interrupt.
--
1.9.1
--
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