On 02/26/2015 01:21 AM, James Hogan wrote:
> When the UART clock is set slightly under 1.8432MHz, the 8250 driver
> core doesn't permit the 115200 baud rate since it calculates the maximum
> frequency to pass to uart_get_baud_rate by simply dividing the uart
> clock by 16 which yields a value slightly under 115200, even though the
> frequency is close enough for the UART to operate reliably.
>
> Therefore add some tolerance in the calculation of the maximum baud
> rate, specifically +1/128th (~0.8%), to allow the 115200 baud rate to
> be closen for a UART clock as low as 1.8149MHz. For an external divider
> set as close as possible to 1.8432MHz, this should cover every possible
> input frequency above 118.9MHz.
>
> Signed-off-by: James Hogan <james.hogan@xxxxxxxxxx>
> Cc: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
> Cc: Jiri Slaby <jslaby@xxxxxxx>
> Cc: Anton Vorontsov <avorontsov@xxxxxxxxxxxxx>
> Cc: Peter Hurley <peter@xxxxxxxxxxxxxxxxxx>
> Cc: Sebastian Andrzej Siewior <bigeasy@xxxxxxxxxxxxx>
> Cc: linux-serial@xxxxxxxxxxxxxxx
> ---
> As far as I can tell from reading the link below, this tolerance should
> be okay, and it definitely covers the range of input frequencies I
> expect for my particular hardware. I'm open to better ways of handling
> it though.
What is your hardware?
(1814900 + 1814900 / 128) / 16
114317
It is not 115200 but close enough to get you the 115200 baud rate. It
might make sense to increase the tolerance rather than increasing the
the clock but it is up to Peter / Alan to decide.
Sebastian
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