[PATCH] serial: 8250: Tolerate clock variance for max baud rate

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When the UART clock is set slightly under 1.8432MHz, the 8250 driver
core doesn't permit the 115200 baud rate since it calculates the maximum
frequency to pass to uart_get_baud_rate by simply dividing the uart
clock by 16 which yields a value slightly under 115200, even though the
frequency is close enough for the UART to operate reliably.

Therefore add some tolerance in the calculation of the maximum baud
rate, specifically +1/128th (~0.8%), to allow the 115200 baud rate to
be closen for a UART clock as low as 1.8149MHz. For an external divider
set as close as possible to 1.8432MHz, this should cover every possible
input frequency above 118.9MHz.

Signed-off-by: James Hogan <james.hogan@xxxxxxxxxx>
Cc: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
Cc: Jiri Slaby <jslaby@xxxxxxx>
Cc: Anton Vorontsov <avorontsov@xxxxxxxxxxxxx>
Cc: Peter Hurley <peter@xxxxxxxxxxxxxxxxxx>
Cc: Sebastian Andrzej Siewior <bigeasy@xxxxxxxxxxxxx>
Cc: linux-serial@xxxxxxxxxxxxxxx
---
As far as I can tell from reading the link below, this tolerance should
be okay, and it definitely covers the range of input frequencies I
expect for my particular hardware. I'm open to better ways of handling
it though.

https://electronics.stackexchange.com/questions/5850/how-critical-are-uart-frequencies
---
 drivers/tty/serial/8250/8250_core.c | 13 ++++++++-----
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/drivers/tty/serial/8250/8250_core.c b/drivers/tty/serial/8250/8250_core.c
index e3b9570a..5d3d171 100644
--- a/drivers/tty/serial/8250/8250_core.c
+++ b/drivers/tty/serial/8250/8250_core.c
@@ -2537,16 +2537,18 @@ serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
 	struct uart_8250_port *up = up_to_u8250p(port);
 	unsigned char cval;
 	unsigned long flags;
-	unsigned int baud, quot, frac = 0;
+	unsigned int baud, quot, frac = 0, uartclk_hi;
 
 	cval = serial8250_compute_lcr(up, termios->c_cflag);
 
 	/*
-	 * Ask the core to calculate the divisor for us.
+	 * Ask the core to calculate the divisor for us, but tolerate some
+	 * variance (e.g. if the uartclk is only slightly under 1.8432MHz).
 	 */
+	uartclk_hi = port->uartclk + port->uartclk / 128;
 	baud = uart_get_baud_rate(port, termios, old,
 				  port->uartclk / 16 / 0xffff,
-				  port->uartclk / 16);
+				  uartclk_hi / 16);
 	quot = serial8250_get_divisor(up, baud, &frac);
 
 	/*
@@ -3270,15 +3272,16 @@ serial8250_console_write(struct console *co, const char *s, unsigned int count)
 	/* check scratch reg to see if port powered off during system sleep */
 	if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) {
 		struct ktermios termios;
-		unsigned int baud, quot, frac = 0;
+		unsigned int baud, quot, frac = 0, uartclk_hi;
 
 		termios.c_cflag = port->cons->cflag;
 		if (port->state->port.tty && termios.c_cflag == 0)
 			termios.c_cflag = port->state->port.tty->termios.c_cflag;
 
+		uartclk_hi = port->uartclk + port->uartclk / 128;
 		baud = uart_get_baud_rate(port, &termios, NULL,
 					  port->uartclk / 16 / 0xffff,
-					  port->uartclk / 16);
+					  uartclk_hi / 16);
 		quot = serial8250_get_divisor(up, baud, &frac);
 
 		serial8250_set_divisor(port, baud, quot, frac);
-- 
2.0.5

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