On Wed, Jun 29, 2022 at 12:27 PM Chanho Park <chanho61.park@xxxxxxxxxxx> wrote: > Modern exynos SoCs such as Exynos Auto v9 have different internal clock > divider, for example "4". To support this internal value, this adds > clk_div of the s3c64xx_spi_port_config and assign "2" as the default > value to existing s3c64xx_spi_port_config. > > Signed-off-by: Chanho Park <chanho61.park@xxxxxxxxxxx> I don't really see why this divider value should be hard-coded like this. I guess it is some default value, that's OK I guess, then call it: > + * @clk_div: Internal clock divider > + int clk_div; clk_div_default And the documentation should say "clock divider to be used by default unless a specific clock frequency is configured" Yours, Linus Walleij
