On 8/7/20 15:31, Marek Szyprowski wrote:
BPLL clock must not be disabled because it is needed for proper DRAM
operation. This is normally handled by respective memory devfreq driver,
but when that driver is not yet probed or its probe has been deferred the
clock might got disabled what causes board hang. Fix this by calling
clk_prepare_enable() directly from the clock provider driver.
Signed-off-by: Marek Szyprowski <m.szyprowski@xxxxxxxxxxx>
Reviewed-by: Lukasz Luba <lukasz.luba@xxxxxxx>
Tested-by: Lukasz Luba <lukasz.luba@xxxxxxx>
Acked-by: Krzysztof Kozlowski <krzk@xxxxxxxxxx>
Should we add a "Fixes" tag so this commit gets backported down do the
kernels where the DMC driver was introduced?
Fixes: 6e7674c3c6df ("memory: Add DMC driver for Exynos5422") ?
---
drivers/clk/samsung/clk-exynos5420.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index fea33399a632..521cbbfc0987 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -1655,6 +1655,11 @@ static void __init exynos5x_clk_init(struct device_node *np,
* main G3D clock enablement status.
*/
clk_prepare_enable(__clk_lookup("mout_sw_aclk_g3d"));
+ /*
+ * Keep top BPLL mux enabled permanently to ensure that DRAM operates
+ * properly.
+ */
+ clk_prepare_enable(__clk_lookup("mout_bpll"));
I'm going to apply the patch and then these two as a follow up:
https://patchwork.kernel.org/patch/11709097
https://patchwork.kernel.org/patch/11709101
