Re: [PATCH v2] clk: samsung: Keep top BPLL mux on Exynos542x enabled

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

 



Quoting Sylwester Nawrocki (2020-08-11 04:31:30)
> On 8/7/20 15:31, Marek Szyprowski wrote:
> > BPLL clock must not be disabled because it is needed for proper DRAM
> > operation. This is normally handled by respective memory devfreq driver,
> > but when that driver is not yet probed or its probe has been deferred the
> > clock might got disabled what causes board hang. Fix this by calling
> > clk_prepare_enable() directly from the clock provider driver.
> > 
> > Signed-off-by: Marek Szyprowski <m.szyprowski@xxxxxxxxxxx>
> > Reviewed-by: Lukasz Luba <lukasz.luba@xxxxxxx>
> > Tested-by: Lukasz Luba <lukasz.luba@xxxxxxx>
> > Acked-by: Krzysztof Kozlowski <krzk@xxxxxxxxxx>
> 
> Should we add a "Fixes" tag so this commit gets backported down do the 
> kernels where the DMC driver was introduced?
> 
> Fixes: 6e7674c3c6df ("memory: Add DMC driver for Exynos5422") ?

I've recently discovered that stable trees aren't checking for Fixes
tags. So we have to put both a Fixes tag and a Cc stable on the patch
to make sure it gets applied to stable trees. Otherwise it's up to the
robot to figure out that a Fixes tag means maybe this is important.




[Index of Archives]     [Linux SoC Development]     [Linux Rockchip Development]     [Linux for Synopsys ARC Processors]    
  • [Linux on Unisoc (RDA Micro) SoCs]     [Linux Actions SoC]     [Linux USB Development]     [Video for Linux]     [Linux Audio Users]     [Linux SCSI]     [Yosemite News]

  •   Powered by Linux