Hi Marek,
On 8/7/20 10:31 PM, Marek Szyprowski wrote:
> BPLL clock must not be disabled because it is needed for proper DRAM
> operation. This is normally handled by respective memory devfreq driver,
> but when that driver is not yet probed or its probe has been deferred the
> clock might got disabled what causes board hang. Fix this by calling
> clk_prepare_enable() directly from the clock provider driver.
>
> Signed-off-by: Marek Szyprowski <m.szyprowski@xxxxxxxxxxx>
> Reviewed-by: Lukasz Luba <lukasz.luba@xxxxxxx>
> Tested-by: Lukasz Luba <lukasz.luba@xxxxxxx>
> Acked-by: Krzysztof Kozlowski <krzk@xxxxxxxxxx>
> ---
> drivers/clk/samsung/clk-exynos5420.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
> index fea33399a632..521cbbfc0987 100644
> --- a/drivers/clk/samsung/clk-exynos5420.c
> +++ b/drivers/clk/samsung/clk-exynos5420.c
> @@ -1655,6 +1655,11 @@ static void __init exynos5x_clk_init(struct device_node *np,
> * main G3D clock enablement status.
> */
> clk_prepare_enable(__clk_lookup("mout_sw_aclk_g3d"));
> + /*
> + * Keep top BPLL mux enabled permanently to ensure that DRAM operates
> + * properly.
> + */
> + clk_prepare_enable(__clk_lookup("mout_bpll"));
>
> samsung_clk_of_add_provider(np, ctx);
> }
>
Thanks.
Acked-by: Chanwoo Choi <cw00.choi@xxxxxxxxxxx>
--
Best Regards,
Chanwoo Choi
Samsung Electronics
