Hi Krzysztof, On Thu, 22 Nov 2018 at 13:24, Krzysztof Kozlowski <krzk@xxxxxxxxxx> wrote: > > On Tue, 20 Nov 2018 at 19:55, Anand Moon <linux.amoon@xxxxxxxxx> wrote: > > > > As per FSYS usbdrd_phy clk setting CLK_SCLK_USBD300/1 binds > > to SUSPEND_CLK so correct update the suspend clk. > > > > Signed-off-by: Anand Moon <linux.amoon@xxxxxxxxx> > > --- > > [0] https://lkml.org/lkml/2017/10/6/12 > > changes from previous patch > > fix the order of clk and update the commit message > > > > FSYS block show in user manual > > > > CLKMUX_USBDRD300/1----CLKDIV_USBDRD300/1----SCLK_USBDRD300/1-----SUSPEND_CLK > > | > > |--CLKDIV_USBPHY300/1----SCLK_USBPHY300/1-----USBDRD30_PHY_0/1 > > Your new clock - SCLK_USBD301 - is not mentioned here. I don't get the > reason behind this change. > > Best regards, > Krzysztof > My patch was based on following block diagram. [0] https://imgur.com/a/fmpk9aR But looks like I am bit wrong with this patch again. Sorry for the noise. Best Regards -Anand
