Re: [PATCHv2] ARM: dts: exynos: update the usbdrd_phy suspend clk

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Hi Krzysztof,

On Thu, 22 Nov 2018 at 13:24, Krzysztof Kozlowski <krzk@xxxxxxxxxx> wrote:
>
> On Tue, 20 Nov 2018 at 19:55, Anand Moon <linux.amoon@xxxxxxxxx> wrote:
> >
> > As per FSYS usbdrd_phy clk setting CLK_SCLK_USBD300/1 binds
> > to SUSPEND_CLK so correct update the suspend clk.
> >
> > Signed-off-by: Anand Moon <linux.amoon@xxxxxxxxx>
> > ---
> > [0] https://lkml.org/lkml/2017/10/6/12
> > changes from previous patch
> > fix the order of clk and update the commit message
> >
> > FSYS block show in user manual
> >
> > CLKMUX_USBDRD300/1----CLKDIV_USBDRD300/1----SCLK_USBDRD300/1-----SUSPEND_CLK
> >                    |
> >                    |--CLKDIV_USBPHY300/1----SCLK_USBPHY300/1-----USBDRD30_PHY_0/1
>
> Your new clock - SCLK_USBD301 - is not mentioned here. I don't get the
> reason behind this change.
>
> Best regards,
> Krzysztof
>

As far as I could figure your from fsys clk  structure

CLK_SCLK_USBD300/1              SUSPEND_CLK
CLK_SCLK_USBPHY300/1          PHY CLK
CLK_USBD300/1                        DWC3 CLK

I sill have some dough from the schematic of Odroid XU4
we have two clk *USB_CLK* and *RTC_CLK* which is not
configure and used.

Best Regards
-Anand



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