Hi Andy Shevchenko,
Thanks for the feedback.
> -----Original Message-----
> From: andy.shevchenko@xxxxxxxxx <andy.shevchenko@xxxxxxxxx>
> Sent: Monday, March 6, 2023 11:36 PM
> To: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> Cc: Linus Walleij <linus.walleij@xxxxxxxxxx>; Philipp Zabel
> <p.zabel@xxxxxxxxxxxxxx>; Geert Uytterhoeven <geert+renesas@xxxxxxxxx>;
> Thierry Reding <thierry.reding@xxxxxxxxx>; Uwe Kleine-König <u.kleine-
> koenig@xxxxxxxxxxxxxx>; linux-pwm@xxxxxxxxxxxxxxx; linux-renesas-
> soc@xxxxxxxxxxxxxxx; linux-gpio@xxxxxxxxxxxxxxx; Chris Paterson
> <Chris.Paterson2@xxxxxxxxxxx>; Prabhakar Mahadev Lad <prabhakar.mahadev-
> lad.rj@xxxxxxxxxxxxxx>
> Subject: Re: [PATCH v6 06/13] drivers: pinctrl: renesas: Add RZ/G2L POEG
> driver support
>
> Mon, Mar 06, 2023 at 09:00:07AM +0000, Biju Das kirjoitti:
> > The output pins of the RZ/G2L general PWM timer (GPT) can be disabled
> > by using the port output enabling function for the GPT (POEG).
> >
> > Add basic support using s/w control through generic pincontrol sysfs
> > to enable/disable output from GPT by registering with RZ/G2L
> > pincontrol driver.
>
> You have wrong Subject prefix.
Oops. Will fix.
>
> ...
>
> > +static void rzg2l_poeg_write(struct rzg2l_poeg_chip *chip, u32 data)
> > +{
> > + iowrite32(data, chip->mmio);
> > +}
> > +
> > +static u32 rzg2l_poeg_read(struct rzg2l_poeg_chip *chip) {
> > + return ioread32(chip->mmio);
> > +}
>
> Why not regmap MMIO?
Some drivers used iowrite32, some uses writel, some uses regmap.
will use regmap for read/write,If the preference is regmap MMIO
as it comes with spinlock for MMIO access.
>
> ...
>
> > +static struct platform_driver rzg2l_poeg_driver = {
> > + .driver = {
> > + .name = "rzg2l-poeg",
> > + .of_match_table = of_match_ptr(rzg2l_poeg_of_table),
>
> Why do you need of_match_ptr()?
Not needed. Will remove it.
Cheers,
Biju
>
> > + },
> > + .probe = rzg2l_poeg_probe,
> > + .remove = rzg2l_poeg_remove,
> > +};
>
> --
> With Best Regards,
> Andy Shevchenko
>
