> Subject: Re: [PATCH RFC 0/8] Add RZ/G2L MTU3a MFD and Counter driver
>
> On Sat, Oct 01, 2022 at 06:03:37PM +0000, Biju Das wrote:
> > > What is the configuration when 32-bit phase counting mode is
> selected?
> >
> > LWA Bit (MTU1/MTU2 Combination Longword Access Control) needs to set
> for 32-bit phase counting mode.
> >
> > b0 LWA 0 R/W MTU1/MTU2 Combination Longword Access Control
> > 0: 16-bit access is enabled.
> > 1: 32-bit access is enabled.
> >
> > > Does MTCLKA and MTCLKB serve as the counting signals in this case,
> >
> > For 16-bit and 32-bit counting signals same. We can set
> >
> > 1) MTU 1 and MTU2 signals as MTCLKA and MTCLKB
> >
> > Or
> >
> > 2) MTU 1 signal as MTCLKA and MTCLKB and MTU2 signals as MTCLKC and
> > MTCLKD
>
> I'm having trouble understanding this case. If 32-bit access is
> enabled by setting the LWA bit, and the MTU1 signals are configured as
> MTCLKA and MTCLKB while at the same time the MTU2 signals are
> configured as MTCLKC and MTCLKD, how is the 32-bit count value
> determined -- wouldn't
> MTU1 and MTU2 be counting independently if they each had separate
> input clocks fed to them?
It is taken care by the HW. We just configure the register as mentioned below
and hardware provide counter values once feeding the signals to
either
{MTCLKA and MTCLKB} for both MTU1 and MTU2
or
MTU1{MTCLKA and MTCLKB} and MTU2{MTCLKC and MTCLKD}
The signal feeding is same for 16-bit and 32-bit phase modes.
Note:- I haven't tested 32-bit mode yet.
Cheers,
Biju
>
> >
> >
> > b1 PHCKSEL 1 R/W External Input Phase Clock Select Selects the
> > external clock pin for phase counting mode.
> > 0: MTCLKA and MTCLKB are selected for the external phase clock.
> > 1: MTCLKC and MTCLKD are selected for the external phase clock
> >
> > > with overflows on the MTU1 register incrementing the MTU2
> register?
> >
> > No. that won't happen as we need to use different register for Long
> > word access
> >
> > These are the regiters used
> > 16-bit:- TCNT{MTU1,MTU2}, TGRA{MTU1,MTU2}, and TGRB{MTU1,MTU2},
> > 32-bit:- MTU1.TCNT_1_LW, MTU1.TGRA_1_LW and MTU1.TGRB_1_LW
> >
> > Counter in MTU1 MTU1.TCNT Word MTU1.TCNT_1_LW Longword
> > Counter in MTU2 MTU2.TCNT Word
> >
> > General register A in MTU1 MTU1.TGRA Word MTU1.TGRA_1_LW Longword
> > General register A in MTU2 MTU2.TGRA Word
> >
> > General register B in MTU1 MTU1.TGRB Word MTU1.TGRB_1_LW Longword
> > General register B in MTU2 MTU2.TGRB Word
> >
> > Cheers,
> > Biju
