Hi Geert
Thank you for your review
> > @@ -75,6 +77,7 @@ static const struct cpg_core_clk r8a77995_core_clks[] __initconst = {
> > DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000),
> >
> > /* Core Clock Outputs */
> > + DEF_FIXED("za2", R8A77995_CLK_ZA2, CLK_PLL0D24, 1, 1),
>
> This does not match the Hardware User's Manual (Rev. 2.20):
> 1. ZA2 is not a fixed clock, but can be controlled through the ZA2CKCR
> register. Adding support for that requires writing a custom clock
> driver.
> Of course we can consider it a fixed clock initially, and make it
> configurable later, when time permits.
> 2. The parent clock is either PLL0D3 or S0, with a configurable
> post-divider of 2 or 4, yielding 200, 250, 400, or 500[*] MHz.
> Using plain PLL0D24 would mean a post-divider of 8, yielding
> 125 MHz, which is not documented as a supported value.
>
> [*] Using the default would mean:
>
> DEF_FIXED("za2", R8A77995_CLK_ZA2, CLK_PLL0D3, 4, 1);
Oops, I had checked E3 block.
Thank you pointing it. will fix in v2
Thank you for your help !!
Best regards
---
Kuninori Morimoto
