Hi Geert
> > This does not match the Hardware User's Manual (Rev. 2.20):
> > 1. ZA2 is not a fixed clock, but can be controlled through the ZA2CKCR
> > register. Adding support for that requires writing a custom clock
> > driver.
> > Of course we can consider it a fixed clock initially, and make it
> > configurable later, when time permits.
> > 2. The parent clock is either PLL0D3 or S0, with a configurable
> > post-divider of 2 or 4, yielding 200, 250, 400, or 500[*] MHz.
> > Using plain PLL0D24 would mean a post-divider of 8, yielding
> > 125 MHz, which is not documented as a supported value.
> >
> > [*] Using the default would mean:
> >
> > DEF_FIXED("za2", R8A77995_CLK_ZA2, CLK_PLL0D3, 4, 1);
PLL0 * 1/3 = 1GHz.
And default ZA2 on D3 is 500MHz thus it will be below
but am I misunderstanding ?
- DEF_FIXED("za2", R8A77995_CLK_ZA2, CLK_PLL0D3, 4, 1);
+ DEF_FIXED("za2", R8A77995_CLK_ZA2, CLK_PLL0D3, 2, 1);
Thank you for your help !!
Best regards
---
Kuninori Morimoto
