On Thu, 19 Dec 2024, Lukas Wunner wrote: > On Thu, Dec 19, 2024 at 08:43:57AM +0900, Krzysztof Wilczy??ski wrote: > > > > The GENMASK() macro used herein specifies 0 as lowest bit, even though > > > > the Supported Link Speeds Vector ends at bit 1. This is done on purpose > > > > to avoid a GENMASK(0, 1) macro if Max Link Speed is zero. That macro > > > > would be invalid as the lowest bit is greater than the highest bit. > > > > Ilpo has witnessed a zero Max Link Speed on Root Complex Integrated > > > > Endpoints in particular, so it does occur in practice. > > > > > > Thanks for adding this extra information. > > > > > > I'd also add reference to r6.2 section 7.5.3 which states those registers > > > are required for RPs, Switch Ports, Bridges, and Endpoints _that are not > > > RCiEPs_. My reading is that implies they're not required from RCiEPs. > > > > Let me know how you would like to update the commit message. I will do it > > directly on the branch. > > FWIW, I edited the commit message like this on my local branch: > > -Endpoints in particular, so it does occur in practice. > +Endpoints in particular, so it does occur in practice. (The Link > +Capabilities Register is optional on RCiEPs per PCIe r6.2 sec 7.5.3.) > > In other words, I just added the sentence in parentheses. > But maybe Ilpo has another wording preference... :) Your wording is good summary for the real substance that is the spec itself. :-) -- i.
