On 17/10/2022 08:43, Lorenzo Pieralisi wrote:
On Tue, Oct 11, 2022 at 05:47:50PM +0100, Jon Hunter wrote:
On 11/10/2022 17:16, Pali Rohár wrote:
...
I see, this is stupid mistake. PCIe config read and write operations
needs to be 4-byte aligned, so normally it is done by calculating 4-byte
aligned base address and then using appropriate cpu load/store
instruction to access just defined size/offset of 4-byte config space
register.
pci-tegra.c is using common helper functions pci_generic_config_read()
and pci_generic_config_write(), which expects final address with offset,
and not 4-byte aligned address.
I'm not sure what should be the proper fix, but for me it looks like
that pci_generic_config_read() and pci_generic_config_write() could be
adjusted to handle it.
In any case, above patch is a regressions and I see there two options
for now:
1) Reverting that patch
2) Adding "offset |= where & 0x3;" after the PCI_CONF1_EXT_ADDRESS()
macro to set also lower 2 bits of accessed register.
Jon, Lorenzo, what do you think? Could you test if 2) is working fine?
I tested 'offset |= where & 0xff' which is essentially the same as the above
and that is working and so I am sure that the above works too. However, I do
wonder if reverting is simpler because we already have a '&
~PCI_CONF1_ENABLE' and now adding '| where & 0x3' seems to diminish the
value of this change.
Hi Jon,
it is unfortunate but I think we should proceed with a revert, please
send it and I shall ask Bjorn to send it for one of the upcoming -rcX.
I have sent a revert for this change.
Thanks
Jon
--
nvpublic
