On 28/09/2022 13:19, Pali Rohár wrote:
Simplify pci-tegra.c driver code and use new PCI_CONF1_EXT_ADDRESS() macro
for accessing PCI config space.
Signed-off-by: Pali Rohár <pali@xxxxxxxxxx>
---
Please look also at this related patch:
https://patchwork.kernel.org/project/linux-pci/patch/20220911113216.14892-1-pali@xxxxxxxxxx/
---
drivers/pci/controller/pci-tegra.c | 11 +++--------
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c
index 5df90d183526..c9924e75e597 100644
--- a/drivers/pci/controller/pci-tegra.c
+++ b/drivers/pci/controller/pci-tegra.c
@@ -417,13 +417,6 @@ static inline u32 pads_readl(struct tegra_pcie *pcie, unsigned long offset)
* address (access to which generates correct config transaction) falls in
* this 4 KiB region.
*/
-static unsigned int tegra_pcie_conf_offset(u8 bus, unsigned int devfn,
- unsigned int where)
-{
- return ((where & 0xf00) << 16) | (bus << 16) | (PCI_SLOT(devfn) << 11) |
- (PCI_FUNC(devfn) << 8) | (where & 0xff);
-}
-
static void __iomem *tegra_pcie_map_bus(struct pci_bus *bus,
unsigned int devfn,
int where)
@@ -445,7 +438,9 @@ static void __iomem *tegra_pcie_map_bus(struct pci_bus *bus,
unsigned int offset;
u32 base;
- offset = tegra_pcie_conf_offset(bus->number, devfn, where);
+ offset = PCI_CONF1_EXT_ADDRESS(bus->number, PCI_SLOT(devfn),
+ PCI_FUNC(devfn), where) &
+ ~PCI_CONF1_ENABLE;
/* move 4 KiB window to offset within the FPCI region */
base = 0xfe100000 + ((offset & ~(SZ_4K - 1)) >> 8);
Our PCIe test on Tegra124 Jetson TK1 is currently failing on -next and
bisect points to this commit. Looking at bit closer, the problem appears
to be the PCI_CONF1_REG_MASK which has a value of 0xfc. Before this
patch was applied a mask of 0xff was applied to the lower 8-bits of
'where' and now it is 0xfc. So this does not work for Tegra as it is.
Let me know if you have any thoughts?
Jon
--
nvpublic
