Hi John,
On Aug 13, 2009, at 5:14 PM, John Sarman wrote:
<snip from omap 35xx page>
General Purpose Memory Controller (GPMC)
* 16-bit Wide Multiplexed Address/Data Bus
* Up to 8 Chip Select Pins With 128M-Byte Address Space per Chip
Select Pin
* Glueless Interface to NOR Flash, NAND Flash (With ECC Hamming
Code Calculation), SRAM and Pseudo-SRAM
* Flexible Asynchronous Protocol Control for Interface to Custom
Logic (FPGA, CPLD, ASICs, etc.)
* Nonmultiplexed Address/Data Mode (Limited 2K-Byte Address Space)
</snip from omap 35xx page>
Thanks for the info, I've read that section on the GPMC. I'm going to
attempt this in stages. First I'll implement a simple protocol between
the OMAP and the FPGA, e.g. use GPIOs to signal read and write
operations, and the serial UART0 to transfer data to a memory location
for the FPGA to process and return the result.
Since the TI OMAP uses 1.8v signalling, I can directly interface it
with the Virtex-5 and get a simple prototype up and running.
After that, create a TI OMAP GPMC to PLB v4.6 Bus Bridge, to make the
GPMC requests appear in the FPGA PLB bus, so that it can access the
FPGA devices and peripherals connected to the PLB bus. I'm using the
gumstix Overo for these tests, and the GPMC signals are not available
on the Palo43 or summit expansion boards. It is available on the Overo
J4/J6 connector though, but that needs a custom board to bring those
signals out.
Do you know if any other TI OMAP 35xx development board exposes the
GPMC connectors? I just want to finish the software/firmware part
before starting work on a custom expansion board.
Best regards,
Elvis
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