On Wed, Aug 12, 2009 at 10:13 AM, Elvis Dowson<elvis.dowson@xxxxxxx> wrote:
> Hi John,
>
> On Aug 12, 2009, at 4:54 PM, John Sarman wrote:
>
>> Use LVCMOS at 1.8V if you can not use 1.8 V (get another FPGA, just
>> kidding) then you will need a buffer (level translator) between them.
>
> Thanks for the info. I think I have support for LVCMOS at 1.8v on the
> Virtex-5. :-)
>
> BTW, what about the GPMC controller, does same signal I/O standard apply?
LVCMOS Single ended standard IO for low power low voltage.
LVTTL Single ended standard IO for compatiblity with older
technologies, can sink souce more current and have higher voltage
tolerances.
HSTL differential pair, no good for GPMC
SSTL SSTL_18 Series Stub Terminated, used with DDR II memory;
requires Vddq = 1.8v, Vt = 0.5 x Vddq. Worth doing research to see if
this would make sense for the GPMC.
GTL is a backplane Ghz IO only swings to 1.2V
PCI for interfacing with the PCI bus, so again probably not.
I would look into SSTL if you are going to interface the FPGA with the
OMAP as if the FPGA appears as a memory device. Not 100% sure though.
<snip from omap 35xx page>
General Purpose Memory Controller (GPMC)
* 16-bit Wide Multiplexed Address/Data Bus
* Up to 8 Chip Select Pins With 128M-Byte Address Space per Chip Select Pin
* Glueless Interface to NOR Flash, NAND Flash (With ECC Hamming
Code Calculation), SRAM and Pseudo-SRAM
* Flexible Asynchronous Protocol Control for Interface to Custom
Logic (FPGA, CPLD, ASICs, etc.)
* Nonmultiplexed Address/Data Mode (Limited 2K-Byte Address Space)
</snip from omap 35xx page>
John
>
> Best regards,
>
> Elvis
>
>
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