Re: TI OMAP 3503 GPIO signal I/O standard for interfacing with FPGA

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Hi John,

On Aug 12, 2009, at 4:54 PM, John Sarman wrote:

Use LVCMOS at 1.8V  if you can not use 1.8 V (get another FPGA, just
kidding)  then you will need a buffer (level translator) between them.

Thanks for the info. I think I have support for LVCMOS at 1.8v on the Virtex-5. :-)

BTW, what about the GPMC controller, does same signal I/O standard apply?

Best regards,

Elvis

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