This patch add the OMAP3 mux configurations from TI (Anand Gadiyar).
Added OMAP2/OMAP3 multi-architecture support - and more
important - only the required pin-tables for the current
configuration are build.
Signed-off-by: Klaus Pedersen <klaus.k.pedersen@xxxxxxxxx>
---
arch/arm/mach-omap2/mux.c | 144 ++++++++++++++++++++++++++++++++++++++-
include/asm-arm/arch-omap/mux.h | 136 ++++++++++++++++++++++++++++++++++++-
2 files changed, 275 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index cf4720f..afd8ece 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -1,8 +1,9 @@
/*
* linux/arch/arm/mach-omap2/mux.c
*
- * OMAP1 pin multiplexing configurations
+ * OMAP2 and OMAP3 pin multiplexing configurations
*
+ * Copyright (C) 2007 Texas Instruments Inc.
* Copyright (C) 2003 - 2005 Nokia Corporation
*
* Written by Tony Lindgren <tony.lindgren@xxxxxxxxx>
@@ -34,6 +35,8 @@
/* NOTE: See mux.h for the enumeration */
+#if defined(CONFIG_ARCH_OMAP24XX)
+
struct pin_config __initdata_or_module omap24xx_pins[] = {
/*
* description mux mux pull pull debug
@@ -107,6 +110,9 @@ MUX_CFG_24XX("G4_242X_DMAREQ3", 0x073, 2, 0, 0, 1)
MUX_CFG_24XX("D3_242X_DMAREQ4", 0x072, 2, 0, 0, 1)
MUX_CFG_24XX("E3_242X_DMAREQ5", 0x071, 2, 0, 0, 1)
+/* TSC IRQ */
+MUX_CFG_24XX("P20_24XX_TSC_IRQ", 0x108, 0, 0, 0, 1)
+
/* UART3 */
MUX_CFG_24XX("K15_24XX_UART3_TX", 0x118, 0, 0, 0, 1)
MUX_CFG_24XX("K14_24XX_UART3_RX", 0x119, 0, 0, 0, 1)
@@ -205,12 +211,144 @@ MUX_CFG_24XX("AC10_2430_MCBSP2_FSX_OFF",0x012E, 0, 0, 0, 1)
MUX_CFG_24XX("AD16_2430_MCBSP2_CLX_OFF",0x012F, 0, 0, 0, 1)
MUX_CFG_24XX("AE13_2430_MCBSP2_DX_OFF", 0x0130, 0, 0, 0, 1)
MUX_CFG_24XX("AD13_2430_MCBSP2_DR_OFF", 0x0131, 0, 0, 0, 1)
+
+/* 2430 UART3 & GPIO */
+MUX_CFG_24XX("L2_2430_UART_IRTX", 0x0128, 0, 0, 0, 1)
+MUX_CFG_24XX("K2_2430_GPIO_103", 0x0127, 3, 0, 0, 1)
+MUX_CFG_24XX("L2_2430_GPIO_104", 0x0128, 3, 0, 0, 1)
+};
+#endif
+
+#if defined(CONFIG_ARCH_OMAP34XX)
+
+struct pin_config __initdata_or_module omap34xx_pins[] = {
+/*
+ * description mux mux pull pull inp dbg
+ * offset mode ena type ena
+ */
+
+/* PHY - HSUSB: 12-pin ULPI PHY: Port 1*/
+MUX_CFG_34XX("Y9_3430_USB1HS_PHY_STP", 0x5d8, 3, 1, 1, 0, 1)
+MUX_CFG_34XX("Y8_3430_USB1HS_PHY_CLK", 0x5da, 3, 0, 0, 0, 1)
+MUX_CFG_34XX("W13_3430_USB1HS_PHY_D0", 0x5dc, 3, 0, 0, 1, 1)
+MUX_CFG_34XX("W12_3430_USB1HS_PHY_D1", 0x5de, 3, 0, 0, 1, 1)
+MUX_CFG_34XX("W11_3430_USB1HS_PHY_D2", 0x5e0, 3, 0, 0, 1, 1)
+MUX_CFG_34XX("Y13_3430_USB1HS_PHY_D7", 0x5e2, 3, 0, 0, 1, 1)
+MUX_CFG_34XX("W9_3430_USB1HS_PHY_D4", 0x5e4, 3, 0, 0, 1, 1)
+MUX_CFG_34XX("Y12_3430_USB1HS_PHY_D5", 0x5e6, 3, 0, 0, 1, 1)
+MUX_CFG_34XX("W8_3430_USB1HS_PHY_D6", 0x5e8, 3, 0, 0, 1, 1)
+MUX_CFG_34XX("Y11_3430_USB1HS_PHY_D3", 0x5ea, 3, 0, 0, 1, 1)
+MUX_CFG_34XX("AA14_3430_USB1HS_PHY_DIR",0x5ec, 3, 0, 0, 1, 1)
+MUX_CFG_34XX("AA11_3430_USB1HS_PHY_NXT",0x5ee, 3, 0, 0, 1, 1)
+
+/* PHY - HSUSB: 12-pin ULPI PHY: Port 2*/
+MUX_CFG_34XX("AA8_3430_USB2HS_PHY_CLK", 0x5f0, 3, 0, 0, 0, 1)
+MUX_CFG_34XX("AA10_3430_USB2HS_PHY_STP",0x5f2, 3, 1, 1, 0, 1)
+MUX_CFG_34XX("AA9_3430_USB2HS_PHY_DIR", 0x5f4, 3, 0, 0, 1, 1)
+MUX_CFG_34XX("AB11_3430_USB2HS_PHY_NXT",0x5f6, 3, 0, 0, 1, 1)
+MUX_CFG_34XX("AB10_3430_USB2HS_PHY_D0", 0x5f8, 3, 0, 0, 1, 1)
+MUX_CFG_34XX("AB9_3430_USB2HS_PHY_D1", 0x5fa, 3, 0, 0, 1, 1)
+MUX_CFG_34XX("W3_3430_USB2HS_PHY_D2", 0x1d4, 3, 0, 0, 1, 1)
+MUX_CFG_34XX("T2_3430_USB2HS_PHY_D7", 0x1d6, 3, 0, 0, 1, 1)
+MUX_CFG_34XX("T3_3430_USB2HS_PHY_D4", 0x1d8, 3, 0, 0, 1, 1)
+MUX_CFG_34XX("R3_3430_USB2HS_PHY_D5", 0x1da, 3, 0, 0, 1, 1)
+MUX_CFG_34XX("R4_3430_USB2HS_PHY_D6", 0x1dc, 3, 0, 0, 1, 1)
+MUX_CFG_34XX("T4_3430_USB2HS_PHY_D3", 0x1de, 3, 0, 0, 1, 1)
+
+/* TLL - HSUSB: 12-pin TLL Port 1*/
+MUX_CFG_34XX("Y9_3430_USB1HS_TLL_STP", 0x5d8, 6, 0, 0, 1, 1)
+MUX_CFG_34XX("Y8_3430_USB1HS_TLL_CLK", 0x5da, 6, 1, 0, 1, 1)
+MUX_CFG_34XX("W13_3430_USB1HS_TLL_D0", 0x5dc, 6, 1, 0, 1, 1)
+MUX_CFG_34XX("W12_3430_USB1HS_TLL_D1", 0x5de, 6, 1, 0, 1, 1)
+MUX_CFG_34XX("W11_3430_USB1HS_TLL_D2", 0x5e0, 6, 1, 0, 1, 1)
+MUX_CFG_34XX("Y13_3430_USB1HS_TLL_D7", 0x5e2, 6, 1, 0, 1, 1)
+MUX_CFG_34XX("W9_3430_USB1HS_TLL_D4", 0x5e4, 6, 1, 0, 1, 1)
+MUX_CFG_34XX("Y12_3430_USB1HS_TLL_D5", 0x5e6, 6, 1, 0, 1, 1)
+MUX_CFG_34XX("W8_3430_USB1HS_TLL_D6", 0x5e8, 6, 1, 0, 1, 1)
+MUX_CFG_34XX("Y11_3430_USB1HS_TLL_D3", 0x5ea, 6, 1, 0, 1, 1)
+MUX_CFG_34XX("AA14_3430_USB1HS_TLL_DIR",0x5ec, 6, 1, 0, 1, 1)
+MUX_CFG_34XX("AA11_3430_USB1HS_TLL_NXT",0x5ee, 6, 1, 0, 1, 1)
+
+/* TLL - HSUSB: 12-pin TLL Port 2*/
+MUX_CFG_34XX("AA8_3430_USB2HS_TLL_CLK", 0x5f0, 6, 1, 0, 1, 1)
+MUX_CFG_34XX("AA10_3430_USB2HS_TLL_STP",0x5f2, 6, 0, 0, 1, 1)
+MUX_CFG_34XX("AA9_3430_USB2HS_TLL_DIR", 0x5f4, 6, 1, 0, 1, 1)
+MUX_CFG_34XX("AB11_3430_USB2HS_TLL_NXT",0x5f6, 6, 1, 0, 1, 1)
+MUX_CFG_34XX("AB10_3430_USB2HS_TLL_D0", 0x5f8, 6, 1, 0, 1, 1)
+MUX_CFG_34XX("AB9_3430_USB2HS_TLL_D1", 0x5fa, 6, 1, 0, 1, 1)
+MUX_CFG_34XX("W3_3430_USB2HS_TLL_D2", 0x1d4, 2, 1, 0, 1, 1)
+MUX_CFG_34XX("T2_3430_USB2HS_TLL_D7", 0x1d6, 2, 1, 0, 1, 1)
+MUX_CFG_34XX("T3_3430_USB2HS_TLL_D4", 0x1d8, 2, 1, 0, 1, 1)
+MUX_CFG_34XX("R3_3430_USB2HS_TLL_D5", 0x1da, 2, 1, 0, 1, 1)
+MUX_CFG_34XX("R4_3430_USB2HS_TLL_D6", 0x1dc, 2, 1, 0, 1, 1)
+MUX_CFG_34XX("T4_3430_USB2HS_TLL_D3", 0x1de, 2, 1, 0, 1, 1)
+
+/* TLL - HSUSB: 12-pin TLL Port 3*/
+MUX_CFG_34XX("AB3_3430_USB3HS_TLL_STP", 0x166, 5, 0, 0, 1, 1)
+MUX_CFG_34XX("AA3_3430_USB3HS_TLL_DIR", 0x168, 5, 1, 0, 1, 1)
+MUX_CFG_34XX("Y3_3430_USB3HS_TLL_NXT", 0x16a, 5, 1, 0, 1, 1)
+MUX_CFG_34XX("AB12_3430_USB3HS_TLL_D4", 0x16c, 5, 1, 0, 1, 1)
+MUX_CFG_34XX("AB13_3430_USB3HS_TLL_D5", 0x16e, 5, 1, 0, 1, 1)
+MUX_CFG_34XX("AA13_3430_USB3HS_TLL_D6", 0x170, 5, 1, 0, 1, 1)
+MUX_CFG_34XX("AA12_3430_USB3HS_TLL_D7", 0x172, 5, 1, 0, 1, 1)
+MUX_CFG_34XX("AA6_3430_USB3HS_TLL_CLK", 0x180, 5, 1, 0, 1, 1)
+MUX_CFG_34XX("Y4_3430_USB3HS_TLL_D1", 0x184, 5, 1, 0, 1, 1)
+MUX_CFG_34XX("AA5_3430_USB3HS_TLL_D0", 0x186, 5, 1, 0, 1, 1)
+MUX_CFG_34XX("Y5_3430_USB3HS_TLL_D2", 0x188, 5, 1, 0, 1, 1)
+MUX_CFG_34XX("W5_3430_USB3HS_TLL_D3", 0x18a, 5, 1, 0, 1, 1)
+
+/* PHY FSUSB: FS Serial PHY 4-pin mode for Port 1*/
+MUX_CFG_34XX("AF10_3430_USB1FS_PHY_MM1_RXDP", 0x5d8, 5, 0, 0, 1, 1)
+MUX_CFG_34XX("AG9_3430_USB1FS_PHY_MM1_RXDM", 0x5ee, 5, 0, 0, 1, 1)
+MUX_CFG_34XX("W13_3430_USB1FS_PHY_MM1_RXRCV", 0x5dc, 5, 0, 0, 1, 1)
+MUX_CFG_34XX("W12_3430_USB1FS_PHY_MM1_TXSE0", 0x5de, 5, 0, 0, 1, 1)
+MUX_CFG_34XX("W11_3430_USB1FS_PHY_MM1_TXDAT", 0x5e0, 5, 0, 0, 1, 1)
+MUX_CFG_34XX("Y11_3430_USB1FS_PHY_MM1_TXEN_N", 0x5ea, 5, 0, 0, 1, 1)
+ /* FSUSB: Serial PHY Port 1 - ISP1301: INT LINE */
+MUX_CFG_34XX("AA14_3430_ISP1301_GPIO22", 0x5EC, 4, 0, 0, 1, 1)
+
+/* PHY FSUSB: FS Serial PHY 4-pin mode for Port 2*/
+MUX_CFG_34XX("AF7_3430_USB2FS_PHY_MM2_RXDP", 0x5f2, 5, 0, 0, 1, 1)
+MUX_CFG_34XX("AH7_3430_USB2FS_PHY_MM2_RXDM", 0x5f6, 5, 0, 0, 1, 1)
+MUX_CFG_34XX("AB10_3430_USB2FS_PHY_MM2_RXRCV", 0x5f8, 5, 0, 0, 1, 1)
+MUX_CFG_34XX("AB9_3430_USB2FS_PHY_MM2_TXSE0", 0x5fa, 5, 0, 0, 1, 1)
+MUX_CFG_34XX("W3_3430_USB2FS_PHY_MM2_TXDAT", 0x1d4, 5, 0, 0, 1, 1)
+MUX_CFG_34XX("T4_3430_USB2FS_PHY_MM2_TXEN_N", 0x1de, 5, 0, 0, 0, 1)
+
+/* PHY FSUSB: FS Serial PHY 4-pin mode for Port 3*/
+MUX_CFG_34XX("AH3_3430_USB3FS_PHY_MM3_RXDP", 0x166, 6, 0, 0, 1, 1)
+MUX_CFG_34XX("AE3_3430_USB3FS_PHY_MM3_RXDM", 0x16a, 6, 0, 0, 1, 1)
+MUX_CFG_34XX("AD1_3430_USB3FS_PHY_MM3_RXRCV", 0x186, 6, 0, 0, 1, 1)
+MUX_CFG_34XX("AE1_3430_USB3FS_PHY_MM3_TXSE0", 0x184, 6, 0, 0, 1, 1)
+MUX_CFG_34XX("AD2_3430_USB3FS_PHY_MM3_TXDAT", 0x188, 6, 0, 0, 1, 1)
+MUX_CFG_34XX("AC1_3430_USB3FS_PHY_MM3_TXEN_N", 0x18a, 6, 0, 0, 0, 1)
+
+/* UART3 */
+MUX_CFG_34XX("R21_3430_UART3_CTS_RCTX", 0x19a, 0, 0, 0, 1, 0)
+MUX_CFG_34XX("T21_3430_UART3_RTS_SD", 0x19c, 0, 0, 0, 1, 0)
+MUX_CFG_34XX("U21_3430_UART3_RX_IRRX", 0x19e, 0, 0, 0, 1, 0)
+MUX_CFG_34XX("V21_3430_UART3_TX_IRTX", 0x1a0, 0, 0, 0, 0, 0)
+
+/* GPIO */
+MUX_CFG_34XX("T21_3430_GPIO164", 0x19c, 4, 0, 0, 1, 0)
+MUX_CFG_34XX("V21_3430_GPIO166", 0x1a0, 4, 0, 0, 1, 0)
};
+#endif
+
int __init omap2_mux_init(void)
{
- omap_mux_register(omap24xx_pins, ARRAY_SIZE(omap24xx_pins));
+#if defined(CONFIG_ARCH_OMAP24XX)
+ if (cpu_is_omap24xx())
+ omap_mux_register(omap24xx_pins, ARRAY_SIZE(omap24xx_pins));
+#endif
+
+#if defined(CONFIG_ARCH_OMAP34XX)
+ if (cpu_is_omap34xx())
+ omap_mux_register(omap34xx_pins, ARRAY_SIZE(omap34xx_pins));
+#endif
+
return 0;
}
-
#endif
+
diff --git a/include/asm-arm/arch-omap/mux.h b/include/asm-arm/arch-omap/mux.h
index 317ea60..1143d9e 100644
--- a/include/asm-arm/arch-omap/mux.h
+++ b/include/asm-arm/arch-omap/mux.h
@@ -112,13 +112,13 @@
* as mux config
*/
#define MUX_CFG_730(desc, mux_reg, mode_offset, mode, \
- pull_bit, pull_status, debug_status)\
+ pull_bit, pull_status, debug_status) \
{ \
.name = desc, \
.debug = debug_status, \
MUX_REG_730(mux_reg, mode_offset, mode) \
PULL_REG_730(mux_reg, pull_bit, pull_status) \
- PU_PD_REG(NA, 0) \
+ PU_PD_REG(NA, 0) \
},
#define MUX_CFG_24XX(desc, reg_offset, mode, \
@@ -132,6 +132,17 @@
.pu_pd_val = pull_mode, \
},
+#define MUX_CFG_34XX(desc, reg_offset, mode, \
+ pull_en, pull_mode, input_en, dbg) \
+{ \
+ .name = desc, \
+ .debug = dbg, \
+ .mux_reg = reg_offset, \
+ .mask = mode, \
+ .pull_val = pull_en, \
+ .pu_pd_val = pull_mode, \
+ .input_en_val = input_en, \
+},
#define PULL_DISABLED 0
#define PULL_ENABLED 1
@@ -157,6 +168,8 @@ struct pin_config {
const char *pu_pd_name;
const unsigned int pu_pd_reg;
const unsigned char pu_pd_val;
+
+ const unsigned char input_en_val;
};
enum omap730_index {
@@ -499,6 +512,9 @@ enum omap24xx_index {
D3_242X_DMAREQ4,
E3_242X_DMAREQ5,
+ /* TSC IRQ */
+ P20_24XX_TSC_IRQ,
+
/* UART3 */
K15_24XX_UART3_TX,
K14_24XX_UART3_RX,
@@ -597,18 +613,134 @@ enum omap24xx_index {
AD16_2430_MCBSP2_CLX_OFF,
AE13_2430_MCBSP2_DX_OFF,
AD13_2430_MCBSP2_DR_OFF,
+
+ /* 2430 UART3 & GPIO */
+ L2_2430_UART_IRTX,
+ K2_2430_GPIO_103,
+ L2_2430_GPIO_104,
+};
+
+enum omap34xx_index {
+
+ /* PHY - HSUSB: 12-pin ULPI PHY: Port 1*/
+ Y9_3430_USB1HS_PHY_STP,
+ Y8_3430_USB1HS_PHY_CLK,
+ W13_3430_USB1HS_PHY_DATA0,
+ W12_3430_USB1HS_PHY_DATA1,
+ W11_3430_USB1HS_PHY_DATA2,
+ Y13_3430_USB1HS_PHY_DATA7,
+ W9_3430_USB1HS_PHY_DATA4,
+ Y12_3430_USB1HS_PHY_DATA5,
+ W8_3430_USB1HS_PHY_DATA6,
+ Y11_3430_USB1HS_PHY_DATA3,
+ AA14_3430_USB1HS_PHY_DIR,
+ AA11_3430_USB1HS_PHY_NXT,
+
+ /* PHY - HSUSB: 12-pin ULPI PHY: Port 2*/
+ AA8_3430_USB2HS_PHY_CLK,
+ AA10_3430_USB2HS_PHY_STP,
+ AA9_3430_USB2HS_PHY_DIR,
+ AB11_3430_USB2HS_PHY_NXT,
+ AB10_3430_USB2HS_PHY_DATA0,
+ AB9_3430_USB2HS_PHY_DATA1,
+ W3_3430_USB2HS_PHY_DATA2,
+ T2_3430_USB2HS_PHY_DATA7,
+ T3_3430_USB2HS_PHY_DATA4,
+ R3_3430_USB2HS_PHY_DATA5,
+ R4_3430_USB2HS_PHY_DATA6,
+ T4_3430_USB2HS_PHY_DATA3,
+
+ /* TLL - HSUSB: 12-pin TLL Port 1*/
+ Y9_3430_USB1HS_TLL_STP,
+ Y8_3430_USB1HS_TLL_CLK,
+ W13_3430_USB1HS_TLL_DATA0,
+ W12_3430_USB1HS_TLL_DATA1,
+ W11_3430_USB1HS_TLL_DATA2,
+ Y13_3430_USB1HS_TLL_DATA7,
+ W9_3430_USB1HS_TLL_DATA4,
+ Y12_3430_USB1HS_TLL_DATA5,
+ W8_3430_USB1HS_TLL_DATA6,
+ Y11_3430_USB1HS_TLL_DATA3,
+ AA14_3430_USB1HS_TLL_DIR,
+ AA11_3430_USB1HS_TLL_NXT,
+
+ /* TLL - HSUSB: 12-pin TLL Port 2*/
+ AA8_3430_USB2HS_TLL_CLK,
+ AA10_3430_USB2HS_TLL_STP,
+ AA9_3430_USB2HS_TLL_DIR,
+ AB11_3430_USB2HS_TLL_NXT,
+ AB10_3430_USB2HS_TLL_DATA0,
+ AB9_3430_USB2HS_TLL_DATA1,
+ W3_3430_USB2HS_TLL_DATA2,
+ T2_3430_USB2HS_TLL_DATA7,
+ T3_3430_USB2HS_TLL_DATA4,
+ R3_3430_USB2HS_TLL_DATA5,
+ R4_3430_USB2HS_TLL_DATA6,
+ T4_3430_USB2HS_TLL_DATA3,
+
+ /* TLL - HSUSB: 12-pin TLL Port 3*/
+ AB3_3430_USB3HS_TLL_STP,
+ AA3_3430_USB3HS_TLL_DIR,
+ Y3_3430_USB3HS_TLL_NXT,
+ AB12_3430_USB3HS_TLL_DATA4,
+ AB13_3430_USB3HS_TLL_DATA5,
+ AA13_3430_USB3HS_TLL_DATA6,
+ AA12_3430_USB3HS_TLL_DATA7,
+ AA6_3430_USB3HS_TLL_CLK,
+ Y4_3430_USB3HS_TLL_DATA1,
+ AA5_3430_USB3HS_TLL_DATA0,
+ Y5_3430_USB3HS_TLL_DATA2,
+ W5_3430_USB3HS_TLL_DATA3,
+
+ /* PHY FSUSB: FS Serial PHY 4-pin mode for Port 1*/
+ AF10_3430_USB1FS_PHY_MM1_RXDP,
+ AG9_3430_USB1FS_PHY_MM1_RXDM,
+ W13_3430_USB1FS_PHY_MM1_RXRCV,
+ W12_3430_USB1FS_PHY_MM1_TXSE0,
+ W11_3430_USB1FS_PHY_MM1_TXDAT,
+ Y11_3430_USB1FS_PHY_MM1_TXEN_N,
+
+ AA14_3430_ISP1301_GPIO22,
+
+ /* PHY FSUSB: FS Serial PHY 4-pin mode for Port 2*/
+ AF7_3430_USB2FS_PHY_MM2_RXDP,
+ AH7_3430_USB2FS_PHY_MM2_RXDM,
+ AB10_3430_USB2FS_PHY_MM2_RXRCV,
+ AB9_3430_USB2FS_PHY_MM2_TXSE0,
+ W3_3430_USB2FS_PHY_MM2_TXDAT,
+ T4_3430_USB2FS_PHY_MM2_TXEN_N,
+
+ /* PHY FSUSB: FS Serial PHY 4-pin mode for Port 3*/
+ AH3_3430_USB3FS_PHY_MM3_RXDP,
+ AE3_3430_USB3FS_PHY_MM3_RXDM,
+ AD1_3430_USB3FS_PHY_MM3_RXRCV,
+ AE1_3430_USB3FS_PHY_MM3_TXSE0,
+ AD2_3430_USB3FS_PHY_MM3_TXDAT,
+ AC1_3430_USB3FS_PHY_MM3_TXEN_N,
+
+ /* UART3 */
+ R21_3430_UART3_CTS_RCTX,
+ T21_3430_UART3_RTS_SD,
+ U21_3430_UART3_RX_IRRX,
+ V21_3430_UART3_TX_IRTX,
+
+ /* GPIO */
+ T21_3430_GPIO164,
+ V21_3430_GPIO166,
};
#ifdef CONFIG_OMAP_MUX
/* setup pin muxing in Linux */
extern int omap1_mux_init(void);
extern int omap2_mux_init(void);
+extern int omap3_mux_init(void);
extern int omap_mux_register(struct pin_config * pins, unsigned long size);
extern int omap_cfg_reg(unsigned long reg_cfg);
#else
/* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */
static inline int omap1_mux_init(void) { return 0; }
static inline int omap2_mux_init(void) { return 0; }
+static inline int omap3_mux_init(void) { return 0; }
static inline int omap_cfg_reg(unsigned long reg_cfg) { return 0; }
#endif
--
1.5.3.3
-
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