Re: AMD SEV-SNP/Intel TDX: validation of memory pages

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On Tue, Feb 16, 2021 at 03:46:36PM +0100, Peter Zijlstra wrote:
> On Tue, Feb 16, 2021 at 06:27:41AM -0800, Andi Kleen wrote:
> > I think the IST solution should at least be explored before
> > dismissing it. It might be simpler than anything else (like
> > using new APIs)
> 
> Have you seen the trainwreck bonzini proposed? The very simplest thing
> is saying no to TDX.

#VE cannot nest until TDINFO. I'm thinking to always switch to
the normal interrupt stack before TDINFO. With that one
it should be equivalent to a non IST #VE, with any
nesting you want supported.

> So how about fixing TDX instead of forcing us to do horrible fragile
> things we all know will end up in tears?

I think we should explore both. If the IST variant is too horrible we
can see about changing TDX. But at least should approach it
with an open mind and see how the code looks like.

-Andi




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